[llvm] [RISCV] Unaligned vec mem => prefer alt opc vec (PR #154153)

[Alexey Bataev via llvm-commits]

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@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
 ; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v | FileCheck %s
 ; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v -slp-threshold=-15 | FileCheck %s --check-prefix=THR15
+; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v,+unaligned-vector-mem | FileCheck %s --check-prefix=UNALIGNED_VEC_MEM
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alexey-bataev wrote:

Does it affect TTI? Particularly, does it affect isLegalMaskedLoadStore? I do not see the difference in the results.
Need to teach TTI, that it is legal to have alignment less than the basic load type. I think you can try to do it for X86, I think it supports it.

https://github.com/llvm/llvm-project/pull/154153