[llvm] [RISCV][GISel] Lower G_ABDS and G_ABDU (PR #155888)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 28 10:13:52 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Shaoce SUN (sunshaoce)
<details>
<summary>Changes</summary>
Implementation follows the `ISD::ABDS` handling in `RISCVTargetLowering::LowerOperation`.
---
Patch is 33.67 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/155888.diff
6 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h (+1)
- (modified) llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp (+33)
- (modified) llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp (+4)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir (+5-4)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir (+209)
- (added) llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir (+310)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
index ea0873f41ebba..7b532d86ac7c1 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
@@ -485,6 +485,7 @@ class LegalizerHelper {
LLVM_ABI LegalizeResult lowerAbsToAddXor(MachineInstr &MI);
LLVM_ABI LegalizeResult lowerAbsToMaxNeg(MachineInstr &MI);
LLVM_ABI LegalizeResult lowerAbsToCNeg(MachineInstr &MI);
+ LLVM_ABI LegalizeResult lowerAbsDiffToMinMax(MachineInstr &MI);
LLVM_ABI LegalizeResult lowerFAbs(MachineInstr &MI);
LLVM_ABI LegalizeResult lowerVectorReduction(MachineInstr &MI);
LLVM_ABI LegalizeResult lowerMemcpyInline(MachineInstr &MI);
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index a4353967698bf..bed4d6d60b177 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -9543,6 +9543,39 @@ LegalizerHelper::lowerAbsToCNeg(MachineInstr &MI) {
return Legalized;
}
+LegalizerHelper::LegalizeResult
+LegalizerHelper::lowerAbsDiffToMinMax(MachineInstr &MI) {
+ assert((MI.getOpcode() == TargetOpcode::G_ABDS ||
+ MI.getOpcode() == TargetOpcode::G_ABDU) &&
+ "Expected G_ABDS or G_ABDU instruction");
+
+ // lhs_frz = freeze(lhs)
+ // rhs_frz = freeze(rhs)
+ Register DstReg = MI.getOperand(0).getReg();
+ Register LHS = MI.getOperand(1).getReg();
+ Register RHS = MI.getOperand(2).getReg();
+ LLT Ty = MRI.getType(LHS);
+ auto LHSFrz = MIRBuilder.buildFreeze(Ty, LHS);
+ auto RHSFrz = MIRBuilder.buildFreeze(Ty, RHS);
+
+ // abds(lhs_frz, rhs_frz)
+ // → sub(smax(lhs_frz, rhs_frz), smin(lhs_frz, rhs_frz))
+ // abdu(lhs_frz, rhs_frz)
+ // → sub(umax(lhs_frz, rhs_frz), umin(lhs_frz, rhs_frz))
+ Register MaxReg, MinReg;
+ if (MI.getOpcode() == TargetOpcode::G_ABDS) {
+ MaxReg = MIRBuilder.buildSMax(Ty, LHSFrz, RHSFrz).getReg(0);
+ MinReg = MIRBuilder.buildSMin(Ty, LHSFrz, RHSFrz).getReg(0);
+ } else {
+ MaxReg = MIRBuilder.buildUMax(Ty, LHSFrz, RHSFrz).getReg(0);
+ MinReg = MIRBuilder.buildUMin(Ty, LHSFrz, RHSFrz).getReg(0);
+ }
+ MIRBuilder.buildSub(DstReg, MaxReg, MinReg);
+
+ MI.eraseFromParent();
+ return Legalized;
+}
+
LegalizerHelper::LegalizeResult LegalizerHelper::lowerFAbs(MachineInstr &MI) {
Register SrcReg = MI.getOperand(1).getReg();
Register DstReg = MI.getOperand(0).getReg();
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 9fd9639e3a1da..20fcc85b7121e 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -488,6 +488,8 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
.lower();
+ getActionDefinitionsBuilder({G_ABDS, G_ABDU}).customFor({s8, s16, s32, s64});
+
getActionDefinitionsBuilder({G_UMAX, G_UMIN, G_SMAX, G_SMIN})
.legalFor(ST.hasStdExtZbb(), {sXLen})
.minScalar(ST.hasStdExtZbb(), 0, sXLen)
@@ -1337,6 +1339,8 @@ bool RISCVLegalizerInfo::legalizeCustom(
return false;
case TargetOpcode::G_ABS:
return Helper.lowerAbsToMaxNeg(MI);
+ case TargetOpcode::G_ABDS:
+ return Helper.lowerAbsDiffToMinMax(MI);
// TODO: G_FCONSTANT
case TargetOpcode::G_CONSTANT: {
const Function &F = MF.getFunction();
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index 9d68a6d72c486..789def015abaa 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -73,12 +73,13 @@
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
#
# DEBUG-NEXT: G_ABDS (opcode 65): 1 type index, 0 imm indices
-# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT:.. the first uncovered type index: 1, OK
+# DEBUG-NEXT:.. the first uncovered imm index: 0, OK
#
# DEBUG-NEXT:G_ABDU (opcode 66): 1 type index, 0 imm indices
-# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT:.. opcode 66 is aliased to 65
+# DEBUG-NEXT:.. the first uncovered type index: 1, OK
+# DEBUG-NEXT:.. the first uncovered imm index: 0, OK
#
# DEBUG-NEXT: G_IMPLICIT_DEF (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir
new file mode 100644
index 0000000000000..7e8038eb8249c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv32.mir
@@ -0,0 +1,209 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o -\
+# RUN: | FileCheck %s --check-prefixes=CHECK,RV32I
+# RUN: llc -mtriple=riscv32 -mattr=+zbb -run-pass=legalizer %s -o -\
+# RUN: | FileCheck %s --check-prefixes=CHECK,RV32ZBB
+
+---
+name: abds_i8
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; RV32I-LABEL: name: abds_i8
+ ; RV32I: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
+ ; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
+ ; RV32I-NEXT: [[FREEZE:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC]]
+ ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT1]](s32)
+ ; RV32I-NEXT: [[FREEZE1:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC1]]
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE]](s16)
+ ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[C]](s32)
+ ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE1]](s16)
+ ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[C]](s32)
+ ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
+ ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]]
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY2]], [[COPY3]]
+ ; RV32I-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
+ ; RV32I-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY2]], [[COPY3]]
+ ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[SELECT1]]
+ ; RV32I-NEXT: $x10 = COPY [[SUB]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32ZBB-LABEL: name: abds_i8
+ ; RV32ZBB: liveins: $x10, $x11
+ ; RV32ZBB-NEXT: {{ $}}
+ ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
+ ; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8
+ ; RV32ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
+ ; RV32ZBB-NEXT: [[FREEZE:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC]]
+ ; RV32ZBB-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT1]](s32)
+ ; RV32ZBB-NEXT: [[FREEZE1:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC1]]
+ ; RV32ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE]](s16)
+ ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 8
+ ; RV32ZBB-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE1]](s16)
+ ; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 8
+ ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]
+ ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
+ ; RV32ZBB-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %3:_(s32) = G_ASSERT_SEXT %1, 8
+ %4:_(s32) = G_ASSERT_SEXT %2, 8
+ %5:_(s8) = G_TRUNC %3(s32)
+ %6:_(s8) = G_TRUNC %4(s32)
+ %7:_(s8) = G_ABDS %5, %6
+ %8:_(s32) = G_ANYEXT %7(s8)
+ $x10 = COPY %8(s32)
+ PseudoRET implicit $x10
+...
+---
+name: abds_i16
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; RV32I-LABEL: name: abds_i16
+ ; RV32I: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
+ ; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 16
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
+ ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT1]](s32)
+ ; RV32I-NEXT: [[FREEZE:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC]]
+ ; RV32I-NEXT: [[FREEZE1:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC1]]
+ ; RV32I-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[FREEZE]](s16)
+ ; RV32I-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[FREEZE1]](s16)
+ ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[SEXT]](s32), [[SEXT1]]
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE]](s16)
+ ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE1]](s16)
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[ANYEXT]], [[ANYEXT1]]
+ ; RV32I-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[SEXT]](s32), [[SEXT1]]
+ ; RV32I-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[ANYEXT]], [[ANYEXT1]]
+ ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[SELECT1]]
+ ; RV32I-NEXT: $x10 = COPY [[SUB]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32ZBB-LABEL: name: abds_i16
+ ; RV32ZBB: liveins: $x10, $x11
+ ; RV32ZBB-NEXT: {{ $}}
+ ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 16
+ ; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 16
+ ; RV32ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
+ ; RV32ZBB-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT1]](s32)
+ ; RV32ZBB-NEXT: [[FREEZE:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC]]
+ ; RV32ZBB-NEXT: [[FREEZE1:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC1]]
+ ; RV32ZBB-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[FREEZE]](s16)
+ ; RV32ZBB-NEXT: [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[FREEZE1]](s16)
+ ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT]], [[SEXT1]]
+ ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT]], [[SEXT1]]
+ ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]
+ ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
+ ; RV32ZBB-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %3:_(s32) = G_ASSERT_SEXT %1, 16
+ %4:_(s32) = G_ASSERT_SEXT %2, 16
+ %5:_(s16) = G_TRUNC %3(s32)
+ %6:_(s16) = G_TRUNC %4(s32)
+ %7:_(s16) = G_ABDS %5, %6
+ %8:_(s32) = G_ANYEXT %7(s16)
+ $x10 = COPY %8(s32)
+ PseudoRET implicit $x10
+...
+---
+name: abds_i32
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; RV32I-LABEL: name: abds_i32
+ ; RV32I: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; RV32I-NEXT: [[FREEZE1:%[0-9]+]]:_(s32) = G_FREEZE [[COPY1]]
+ ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[FREEZE]](s32), [[FREEZE1]]
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[FREEZE]], [[FREEZE1]]
+ ; RV32I-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[FREEZE]](s32), [[FREEZE1]]
+ ; RV32I-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[FREEZE]], [[FREEZE1]]
+ ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[SELECT1]]
+ ; RV32I-NEXT: $x10 = COPY [[SUB]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ;
+ ; RV32ZBB-LABEL: name: abds_i32
+ ; RV32ZBB: liveins: $x10, $x11
+ ; RV32ZBB-NEXT: {{ $}}
+ ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32ZBB-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; RV32ZBB-NEXT: [[FREEZE1:%[0-9]+]]:_(s32) = G_FREEZE [[COPY1]]
+ ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[FREEZE]], [[FREEZE1]]
+ ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[FREEZE]], [[FREEZE1]]
+ ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]
+ ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
+ ; RV32ZBB-NEXT: PseudoRET implicit $x10
+ %1:_(s32) = COPY $x10
+ %2:_(s32) = COPY $x11
+ %3:_(s32) = G_ABDS %1, %2
+ $x10 = COPY %3(s32)
+ PseudoRET implicit $x10
+...
+---
+name: abds_i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: abds_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[COPY]]
+ ; CHECK-NEXT: [[FREEZE1:%[0-9]+]]:_(s32) = G_FREEZE [[COPY1]]
+ ; CHECK-NEXT: [[FREEZE2:%[0-9]+]]:_(s32) = G_FREEZE [[COPY2]]
+ ; CHECK-NEXT: [[FREEZE3:%[0-9]+]]:_(s32) = G_FREEZE [[COPY3]]
+ ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(ugt), [[FREEZE]](s32), [[FREEZE2]]
+ ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[FREEZE1]](s32), [[FREEZE3]]
+ ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[FREEZE1]](s32), [[FREEZE3]]
+ ; CHECK-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP2]](s32), [[ICMP]], [[ICMP1]]
+ ; CHECK-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[FREEZE]], [[FREEZE2]]
+ ; CHECK-NEXT: [[SELECT2:%[0-9]+]]:_(s32) = G_SELECT [[SELECT]](s32), [[FREEZE1]], [[FREEZE3]]
+ ; CHECK-NEXT: [[ICMP3:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[FREEZE]](s32), [[FREEZE2]]
+ ; CHECK-NEXT: [[ICMP4:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[FREEZE1]](s32), [[FREEZE3]]
+ ; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[FREEZE1]](s32), [[FREEZE3]]
+ ; CHECK-NEXT: [[SELECT3:%[0-9]+]]:_(s32) = G_SELECT [[ICMP5]](s32), [[ICMP3]], [[ICMP4]]
+ ; CHECK-NEXT: [[SELECT4:%[0-9]+]]:_(s32) = G_SELECT [[SELECT3]](s32), [[FREEZE]], [[FREEZE2]]
+ ; CHECK-NEXT: [[SELECT5:%[0-9]+]]:_(s32) = G_SELECT [[SELECT3]](s32), [[FREEZE1]], [[FREEZE3]]
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SELECT1]], [[SELECT4]]
+ ; CHECK-NEXT: [[ICMP6:%[0-9]+]]:_(s32) = G_ICMP intpred(ult), [[SELECT1]](s32), [[SELECT4]]
+ ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(s32) = G_SUB [[SELECT2]], [[SELECT5]]
+ ; CHECK-NEXT: [[SUB2:%[0-9]+]]:_(s32) = G_SUB [[SUB1]], [[ICMP6]]
+ ; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
+ ; CHECK-NEXT: $x11 = COPY [[SUB2]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10, implicit $x11
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)
+ %3:_(s32) = COPY $x10
+ %4:_(s32) = COPY $x11
+ %5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)
+ %6:_(s64) = G_ABDS %2, %5
+ %7:_(s32), %8:_(s32) = G_UNMERGE_VALUES %6(s64)
+ $x10 = COPY %7(s32)
+ $x11 = COPY %8(s32)
+ PseudoRET implicit $x10, implicit $x11
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir
new file mode 100644
index 0000000000000..85732b6f9dc1c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-abs-diff-rv64.mir
@@ -0,0 +1,310 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o -\
+# RUN: | FileCheck %s --check-prefixes=RV64I
+# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=legalizer %s -o -\
+# RUN: | FileCheck %s --check-prefixes=RV64ZBB
+
+---
+name: abds_i8
+body: |
+ bb.0.entry:
+ liveins: $x10, $x11
+ ; RV32I-LABEL: name: abds_i8
+ ; RV32I: liveins: $x10, $x11
+ ; RV32I-NEXT: {{ $}}
+ ; RV32I-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32I-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32I-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
+ ; RV32I-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8
+ ; RV32I-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
+ ; RV32I-NEXT: [[FREEZE:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC]]
+ ; RV32I-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT1]](s32)
+ ; RV32I-NEXT: [[FREEZE1:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC1]]
+ ; RV32I-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE]](s16)
+ ; RV32I-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 24
+ ; RV32I-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT]], [[C]](s32)
+ ; RV32I-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[SHL]], [[C]](s32)
+ ; RV32I-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE1]](s16)
+ ; RV32I-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ANYEXT1]], [[C]](s32)
+ ; RV32I-NEXT: [[ASHR1:%[0-9]+]]:_(s32) = G_ASHR [[SHL1]], [[C]](s32)
+ ; RV32I-NEXT: [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(sgt), [[ASHR]](s32), [[ASHR1]]
+ ; RV32I-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[ANYEXT]](s32)
+ ; RV32I-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[ANYEXT1]](s32)
+ ; RV32I-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s32), [[COPY2]], [[COPY3]]
+ ; RV32I-NEXT: [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(slt), [[ASHR]](s32), [[ASHR1]]
+ ; RV32I-NEXT: [[SELECT1:%[0-9]+]]:_(s32) = G_SELECT [[ICMP1]](s32), [[COPY2]], [[COPY3]]
+ ; RV32I-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SELECT]], [[SELECT1]]
+ ; RV32I-NEXT: $x10 = COPY [[SUB]](s32)
+ ; RV32I-NEXT: PseudoRET implicit $x10
+ ; RV32ZBB-LABEL: name: abds_i8
+ ; RV32ZBB: liveins: $x10, $x11
+ ; RV32ZBB-NEXT: {{ $}}
+ ; RV32ZBB-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; RV32ZBB-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; RV32ZBB-NEXT: [[ASSERT_SEXT:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY]], 8
+ ; RV32ZBB-NEXT: [[ASSERT_SEXT1:%[0-9]+]]:_(s32) = G_ASSERT_SEXT [[COPY1]], 8
+ ; RV32ZBB-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT]](s32)
+ ; RV32ZBB-NEXT: [[FREEZE:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC]]
+ ; RV32ZBB-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[ASSERT_SEXT1]](s32)
+ ; RV32ZBB-NEXT: [[FREEZE1:%[0-9]+]]:_(s16) = G_FREEZE [[TRUNC1]]
+ ; RV32ZBB-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE]](s16)
+ ; RV32ZBB-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT]], 8
+ ; RV32ZBB-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[FREEZE1]](s16)
+ ; RV32ZBB-NEXT: [[SEXT_INREG1:%[0-9]+]]:_(s32) = G_SEXT_INREG [[ANYEXT1]], 8
+ ; RV32ZBB-NEXT: [[SMAX:%[0-9]+]]:_(s32) = G_SMAX [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; RV32ZBB-NEXT: [[SMIN:%[0-9]+]]:_(s32) = G_SMIN [[SEXT_INREG]], [[SEXT_INREG1]]
+ ; RV32ZBB-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[SMAX]], [[SMIN]]
+ ; RV32ZBB-NEXT: $x10 = COPY [[SUB]](s32)
+ ; RV32ZBB-NEXT: PseudoRET implicit $x10
+ ; RV64I-LABEL: name: abds_i8
+ ; RV64I: liveins: $x10, $x11
+ ; RV64I-NEXT: {{ $}}
+ ; RV64I-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; RV64I-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; RV64I-NE...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/155888
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