[llvm] 9472225 - [KnownBits] Add operator<<=(unsigned) and operator>>=(unsigned). NFC (#155751)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 28 10:08:31 PDT 2025
Author: Craig Topper
Date: 2025-08-28T10:08:28-07:00
New Revision: 9472225fa6c375ad9964c465c046059dcc386793
URL: https://github.com/llvm/llvm-project/commit/9472225fa6c375ad9964c465c046059dcc386793
DIFF: https://github.com/llvm/llvm-project/commit/9472225fa6c375ad9964c465c046059dcc386793.diff
LOG: [KnownBits] Add operator<<=(unsigned) and operator>>=(unsigned). NFC (#155751)
Add operators to shift left or right and insert unknown bits.
Added:
Modified:
llvm/include/llvm/Support/KnownBits.h
llvm/lib/Analysis/ValueTracking.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/lib/Support/KnownBits.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Support/KnownBits.h b/llvm/include/llvm/Support/KnownBits.h
index e8dc1c2422646..5b693ee587453 100644
--- a/llvm/include/llvm/Support/KnownBits.h
+++ b/llvm/include/llvm/Support/KnownBits.h
@@ -487,6 +487,20 @@ struct KnownBits {
/// Update known bits based on XORing with RHS.
LLVM_ABI KnownBits &operator^=(const KnownBits &RHS);
+ /// Shift known bits left by ShAmt. Shift in bits are unknown.
+ KnownBits &operator<<=(unsigned ShAmt) {
+ Zero <<= ShAmt;
+ One <<= ShAmt;
+ return *this;
+ }
+
+ /// Shift known bits right by ShAmt. Shifted in bits are unknown.
+ KnownBits &operator>>=(unsigned ShAmt) {
+ Zero.lshrInPlace(ShAmt);
+ One.lshrInPlace(ShAmt);
+ return *this;
+ }
+
/// Compute known bits for the absolute value.
LLVM_ABI KnownBits abs(bool IntMinIsPoison = false) const;
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 7fe129b8456f6..83c4c2b5f2e6c 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -727,17 +727,16 @@ static void computeKnownBitsFromCmp(const Value *V, CmpInst::Predicate Pred,
// For those bits in C that are known, we can propagate them to known
// bits in V shifted to the right by ShAmt.
KnownBits RHSKnown = KnownBits::makeConstant(*C);
- RHSKnown.Zero.lshrInPlace(ShAmt);
- RHSKnown.One.lshrInPlace(ShAmt);
+ RHSKnown >>= ShAmt;
Known = Known.unionWith(RHSKnown);
// assume(V >> ShAmt = C)
} else if (match(LHS, m_Shr(m_V, m_ConstantInt(ShAmt))) &&
ShAmt < BitWidth) {
- KnownBits RHSKnown = KnownBits::makeConstant(*C);
// For those bits in RHS that are known, we can propagate them to known
// bits in V shifted to the right by C.
- Known.Zero |= RHSKnown.Zero << ShAmt;
- Known.One |= RHSKnown.One << ShAmt;
+ KnownBits RHSKnown = KnownBits::makeConstant(*C);
+ RHSKnown <<= ShAmt;
+ Known = Known.unionWith(RHSKnown);
}
break;
case ICmpInst::ICMP_NE: {
@@ -1890,10 +1889,9 @@ static void computeKnownBitsFromOperator(const Operator *I,
computeKnownBits(I->getOperand(0), DemandedElts, Known2, Q, Depth + 1);
computeKnownBits(I->getOperand(1), DemandedElts, Known3, Q, Depth + 1);
- Known.Zero =
- Known2.Zero.shl(ShiftAmt) | Known3.Zero.lshr(BitWidth - ShiftAmt);
- Known.One =
- Known2.One.shl(ShiftAmt) | Known3.One.lshr(BitWidth - ShiftAmt);
+ Known2 <<= ShiftAmt;
+ Known3 >>= BitWidth - ShiftAmt;
+ Known = Known2.unionWith(Known3);
break;
}
case Intrinsic::uadd_sat:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 078825f2a9a22..967306ae37f45 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -3868,15 +3868,11 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
if (Opcode == ISD::FSHL) {
- Known.One <<= Amt;
- Known.Zero <<= Amt;
- Known2.One.lshrInPlace(BitWidth - Amt);
- Known2.Zero.lshrInPlace(BitWidth - Amt);
+ Known <<= Amt;
+ Known2 >>= BitWidth - Amt;
} else {
- Known.One <<= BitWidth - Amt;
- Known.Zero <<= BitWidth - Amt;
- Known2.One.lshrInPlace(Amt);
- Known2.Zero.lshrInPlace(Amt);
+ Known <<= BitWidth - Amt;
+ Known2 >>= Amt;
}
Known = Known.unionWith(Known2);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 402a012e8e555..bd543ce1c3851 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -1858,8 +1858,7 @@ bool TargetLowering::SimplifyDemandedBits(
Op->dropFlags(SDNodeFlags::NoWrap);
return true;
}
- Known.Zero <<= ShAmt;
- Known.One <<= ShAmt;
+ Known <<= ShAmt;
// low bits known zero.
Known.Zero.setLowBits(ShAmt);
@@ -2042,8 +2041,7 @@ bool TargetLowering::SimplifyDemandedBits(
if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
Depth + 1))
return true;
- Known.Zero.lshrInPlace(ShAmt);
- Known.One.lshrInPlace(ShAmt);
+ Known >>= ShAmt;
// High bits known zero.
Known.Zero.setHighBits(ShAmt);
@@ -2153,8 +2151,7 @@ bool TargetLowering::SimplifyDemandedBits(
if (SimplifyDemandedBits(Op0, InDemandedMask, DemandedElts, Known, TLO,
Depth + 1))
return true;
- Known.Zero.lshrInPlace(ShAmt);
- Known.One.lshrInPlace(ShAmt);
+ Known >>= ShAmt;
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
@@ -2225,10 +2222,8 @@ bool TargetLowering::SimplifyDemandedBits(
Depth + 1))
return true;
- Known2.One <<= (IsFSHL ? Amt : (BitWidth - Amt));
- Known2.Zero <<= (IsFSHL ? Amt : (BitWidth - Amt));
- Known.One.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
- Known.Zero.lshrInPlace(IsFSHL ? (BitWidth - Amt) : Amt);
+ Known2 <<= (IsFSHL ? Amt : (BitWidth - Amt));
+ Known >>= (IsFSHL ? (BitWidth - Amt) : Amt);
Known = Known.unionWith(Known2);
// Attempt to avoid multi-use ops if we don't need anything from them.
diff --git a/llvm/lib/Support/KnownBits.cpp b/llvm/lib/Support/KnownBits.cpp
index bd08365a3fcdb..8d91f0e95d227 100644
--- a/llvm/lib/Support/KnownBits.cpp
+++ b/llvm/lib/Support/KnownBits.cpp
@@ -372,8 +372,7 @@ KnownBits KnownBits::lshr(const KnownBits &LHS, const KnownBits &RHS,
unsigned BitWidth = LHS.getBitWidth();
auto ShiftByConst = [&](const KnownBits &LHS, unsigned ShiftAmt) {
KnownBits Known = LHS;
- Known.Zero.lshrInPlace(ShiftAmt);
- Known.One.lshrInPlace(ShiftAmt);
+ Known >>= ShiftAmt;
// High bits are known zero.
Known.Zero.setHighBits(ShiftAmt);
return Known;
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 7749ef82ee3dd..7a4dd78703155 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -38676,13 +38676,11 @@ void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
Known = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
if (Opc == X86ISD::VSHLI) {
- Known.Zero <<= ShAmt;
- Known.One <<= ShAmt;
+ Known <<= ShAmt;
// Low bits are known zero.
Known.Zero.setLowBits(ShAmt);
} else if (Opc == X86ISD::VSRLI) {
- Known.Zero.lshrInPlace(ShAmt);
- Known.One.lshrInPlace(ShAmt);
+ Known >>= ShAmt;
// High bits are known zero.
Known.Zero.setHighBits(ShAmt);
} else {
@@ -44518,8 +44516,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
TLO, Depth + 1))
return true;
- Known.Zero <<= ShAmt;
- Known.One <<= ShAmt;
+ Known <<= ShAmt;
// Low bits known zero.
Known.Zero.setLowBits(ShAmt);
@@ -44549,8 +44546,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
TLO, Depth + 1))
return true;
- Known.Zero.lshrInPlace(ShAmt);
- Known.One.lshrInPlace(ShAmt);
+ Known >>= ShAmt;
// High bits known zero.
Known.Zero.setHighBits(ShAmt);
@@ -44598,8 +44594,7 @@ bool X86TargetLowering::SimplifyDemandedBitsForTargetNode(
TLO, Depth + 1))
return true;
- Known.Zero.lshrInPlace(ShAmt);
- Known.One.lshrInPlace(ShAmt);
+ Known >>= ShAmt;
// If the input sign bit is known to be zero, or if none of the top bits
// are demanded, turn this into an unsigned shift right.
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
index f17fecd430a6c..aa030294ff1e5 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
@@ -795,8 +795,7 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Instruction *I,
I->dropPoisonGeneratingFlags();
return I;
}
- Known.Zero.lshrInPlace(ShiftAmt);
- Known.One.lshrInPlace(ShiftAmt);
+ Known >>= ShiftAmt;
if (ShiftAmt)
Known.Zero.setHighBits(ShiftAmt); // high bits known zero.
} else {
@@ -1066,10 +1065,9 @@ Value *InstCombinerImpl::SimplifyDemandedUseBits(Instruction *I,
}
}
- Known.Zero = LHSKnown.Zero.shl(ShiftAmt) |
- RHSKnown.Zero.lshr(BitWidth - ShiftAmt);
- Known.One = LHSKnown.One.shl(ShiftAmt) |
- RHSKnown.One.lshr(BitWidth - ShiftAmt);
+ LHSKnown <<= ShiftAmt;
+ RHSKnown >>= BitWidth - ShiftAmt;
+ Known = LHSKnown.unionWith(RHSKnown);
KnownBitsComputed = true;
break;
}
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