[llvm] [ARM] Add missing optimize compare candidates to isOptimizeCompareCandides (PR #155886)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-arm

Author: AZero13 (AZero13)

<details>
<summary>Changes</summary>

I noticed some were missing when one of the IR I was working on did not optimize it.

---
Full diff: https://github.com/llvm/llvm-project/pull/155886.diff


2 Files Affected:

- (modified) llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp (+8) 
- (added) llvm/test/CodeGen/ARM/peephole-rsb.ll (+19) 


``````````diff
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 9e4dbecc16a87..62ec29142d6a6 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2790,23 +2790,31 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
     [[fallthrough]];
   case ARM::RSBrr:
   case ARM::RSBri:
+  case ARM::RSBrsi:
+  case ARM::RSBrsr:
   case ARM::RSCrr:
   case ARM::RSCri:
   case ARM::ADDrr:
   case ARM::ADDri:
+  case ARM::ADDrsi:
+  case ARM::ADDrsr:
   case ARM::ADCrr:
   case ARM::ADCri:
   case ARM::SUBrr:
   case ARM::SUBri:
+  case ARM::SUBrsr:
+  case ARM::SUBrsi:
   case ARM::SBCrr:
   case ARM::SBCri:
   case ARM::t2RSBri:
   case ARM::t2ADDrr:
   case ARM::t2ADDri:
+  case ARM::t2ADDSrs:
   case ARM::t2ADCrr:
   case ARM::t2ADCri:
   case ARM::t2SUBrr:
   case ARM::t2SUBri:
+  case ARM::t2SUBSrs:
   case ARM::t2SBCrr:
   case ARM::t2SBCri:
   case ARM::ANDrr:
diff --git a/llvm/test/CodeGen/ARM/peephole-rsb.ll b/llvm/test/CodeGen/ARM/peephole-rsb.ll
new file mode 100644
index 0000000000000..91ba40e16761a
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/peephole-rsb.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+v4t -verify-machineinstrs | FileCheck %s
+
+define i8 @abd_ext_i8_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_ext_i8_i8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    lsl r0, r0, #24
+; CHECK-NEXT:    lsl r1, r1, #24
+; CHECK-NEXT:    asr r0, r0, #24
+; CHECK-NEXT:    subs r0, r0, r1, asr #24
+; CHECK-NEXT:    rsbmi r0, r0, #0
+; CHECK-NEXT:    bx lr
+  %aext = sext i8 %a to i64
+  %bext = sext i8 %b to i64
+  %sub = sub i64 %aext, %bext
+  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+  %trunc = trunc i64 %abs to i8
+  ret i8 %trunc
+}

``````````

</details>


https://github.com/llvm/llvm-project/pull/155886