[llvm] [AMDGPU] Determine MCFixupKind in a more general way. NFCI. (PR #155864)

[Jay Foad via llvm-commits]

https://github.com/jayfoad updated https://github.com/llvm/llvm-project/pull/155864

>From 38779aa22b3f8cf6744aae773aea89bef44320f8 Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Thu, 28 Aug 2025 16:48:45 +0100
Subject: [PATCH 1/2] [AMDGPU] Determine MCFixupKind in a more general way.
 NFCI.

---
 .../lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 7 ++-----
 1 file changed, 2 insertions(+), 5 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index 61f673221739a..71a1c2dcb2768 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -695,11 +695,8 @@ void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
     const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
     uint32_t Offset = Desc.getSize();
     assert(Offset == 4 || Offset == 8);
-    auto OpType = Desc.operands()[OpNo].OperandType;
-    MCFixupKind Kind = (STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
-                        OpType == AMDGPU::OPERAND_REG_IMM_INT64)
-                           ? FK_Data_8
-                           : FK_Data_4;
+    unsigned Size = AMDGPU::getOperandSize(Desc, OpNo);
+    MCFixupKind Kind = MCFixup::getDataKindForSize(Size);
     addFixup(Fixups, Offset, MO.getExpr(), Kind, PCRel);
   }
 

>From 0ac94da2fb555333666d4f155dced1722cbc9a3e Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Thu, 28 Aug 2025 16:54:55 +0100
Subject: [PATCH 2/2] One more place

Try to make the logic for encoding the literal better match the logic
for choosing the fixup kind.
---
 llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
index 71a1c2dcb2768..27c3caed5e2df 100644
--- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
+++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
@@ -272,10 +272,7 @@ std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
   int64_t Imm;
   if (MO.isExpr()) {
     if (!MO.getExpr()->evaluateAsAbsolute(Imm))
-      return (STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
-              OpInfo.OperandType == AMDGPU::OPERAND_REG_IMM_INT64)
-                 ? 254
-                 : 255;
+      return AMDGPU::getOperandSize(OpInfo) == 8 ? 254 : 255;
   } else {
     assert(!MO.isDFPImm());