[llvm] AMDGPU: Move some code out of macro for defining regclass decoder (PR #155755)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/155755

>From f5a332168efee95b3ec97ae99674e2455f714402 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 28 Aug 2025 14:37:33 +0900
Subject: [PATCH 1/3] AMDGPU: Move some code out of macro for defining regclass
 decoder

Use a template function for the implementation, and use the macro
to define a constant function pointer with the expected name. Not
sure if there's a cleaner way to do this. This worked out to less
code using variadic templates to forward the arguments, but it added
a noticable ~10 seconds to compilation time on this file.

This will help avoid another copy-paste version of this function
in a future change.
---
 .../Disassembler/AMDGPUDisassembler.cpp       | 25 +++++++++++--------
 1 file changed, 15 insertions(+), 10 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 6a2beeed41dfd..8651ddc89dce2 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -146,17 +146,22 @@ static DecodeStatus decodeDpp8FI(MCInst &Inst, unsigned Val, uint64_t Addr,
     return addOperand(Inst, DAsm->DecoderName(Imm));                           \
   }
 
-// Decoder for registers, decode directly using RegClassID. Imm(8-bit) is
-// number of register. Used by VGPR only and AGPR only operands.
+// Decoder for registers, decode directly using RegClassID. Imm(8-bit) is number
+// of register. Used by VGPR only and AGPR only operands.
+template <unsigned RegClassID>
+static DecodeStatus decodeRegisterClassImpl(MCInst &Inst, unsigned Imm,
+                                            uint64_t /*Addr*/,
+                                            const MCDisassembler *Decoder) {
+  assert(Imm < (1 << 8) && "8-bit encoding");
+  auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);
+  return addOperand(Inst, DAsm->createRegOperand(RegClassID, Imm));
+}
+
+using RegClassDecoder = decltype(&decodeRegisterClassImpl<0>);
+
 #define DECODE_OPERAND_REG_8(RegClass)                                         \
-  static DecodeStatus Decode##RegClass##RegisterClass(                         \
-      MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,                           \
-      const MCDisassembler *Decoder) {                                         \
-    assert(Imm < (1 << 8) && "8-bit encoding");                                \
-    auto DAsm = static_cast<const AMDGPUDisassembler *>(Decoder);              \
-    return addOperand(                                                         \
-        Inst, DAsm->createRegOperand(AMDGPU::RegClass##RegClassID, Imm));      \
-  }
+  static const constexpr RegClassDecoder Decode##RegClass##RegisterClass =     \
+      decodeRegisterClassImpl<AMDGPU::RegClass##RegClassID>;
 
 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm)                           \
   static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,      \

>From 5ccb1a67884484415ef583f41e7a8d8ea88c3b13 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 28 Aug 2025 22:01:06 +0900
Subject: [PATCH 2/3] Use lambda to forward arguments

This seems to cost 4-5 seconds in build time in the file
---
 .../lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 8651ddc89dce2..30f70055d1cae 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -157,11 +157,11 @@ static DecodeStatus decodeRegisterClassImpl(MCInst &Inst, unsigned Imm,
   return addOperand(Inst, DAsm->createRegOperand(RegClassID, Imm));
 }
 
-using RegClassDecoder = decltype(&decodeRegisterClassImpl<0>);
-
 #define DECODE_OPERAND_REG_8(RegClass)                                         \
-  static const constexpr RegClassDecoder Decode##RegClass##RegisterClass =     \
-      decodeRegisterClassImpl<AMDGPU::RegClass##RegClassID>;
+  static const constexpr auto Decode##RegClass##RegisterClass =                \
+      [](auto... args) {                                                       \
+        return decodeRegisterClassImpl<AMDGPU::RegClass##RegClassID>(args...); \
+      };
 
 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm)                           \
   static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,      \

>From e6cd6efb9919c8f51b2937ec5d2fd812567857ec Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 28 Aug 2025 22:06:51 +0900
Subject: [PATCH 3/3] Revert "Use lambda to forward arguments"

This reverts commit 79d03ff80ed3ac9d8f072955c2bae5d7567ff56a.
---
 .../lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index 30f70055d1cae..8651ddc89dce2 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -157,11 +157,11 @@ static DecodeStatus decodeRegisterClassImpl(MCInst &Inst, unsigned Imm,
   return addOperand(Inst, DAsm->createRegOperand(RegClassID, Imm));
 }
 
+using RegClassDecoder = decltype(&decodeRegisterClassImpl<0>);
+
 #define DECODE_OPERAND_REG_8(RegClass)                                         \
-  static const constexpr auto Decode##RegClass##RegisterClass =                \
-      [](auto... args) {                                                       \
-        return decodeRegisterClassImpl<AMDGPU::RegClass##RegClassID>(args...); \
-      };
+  static const constexpr RegClassDecoder Decode##RegClass##RegisterClass =     \
+      decodeRegisterClassImpl<AMDGPU::RegClass##RegClassID>;
 
 #define DECODE_SrcOp(Name, EncSize, OpWidth, EncImm)                           \
   static DecodeStatus Name(MCInst &Inst, unsigned Imm, uint64_t /*Addr*/,      \