[llvm] [BOLT][AArch64] Enabling Inlining for Memcpy for AArch64 in BOLT (PR #154929)

[Sjoerd Meijer via llvm-commits]

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@@ -2597,6 +2597,115 @@ class AArch64MCPlusBuilder : public MCPlusBuilder {
   getInstructionSize(const MCInst &Inst) const override {
     return 4;
   }
+
+  InstructionListType createInlineMemcpy(bool ReturnEnd) const override {
+    return createInlineMemcpy(ReturnEnd, std::nullopt);
+  }
+
+  std::optional<uint64_t>
+  extractMoveImmediate(const MCInst &Inst, MCPhysReg TargetReg) const override {
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sjoerdmeijer wrote:

If we are matching MOVZXi, do we need all these checks? I mean, can there MOVZXI instructions with less than 3 operands? We know the operand 0 is a register? Etc. I guess the only thing we need to match is the opcode==MOVZXi and op0 == TargetReg, in which case we can regurn op1.getImm().

https://github.com/llvm/llvm-project/pull/154929