[llvm] [AArch64] Improve lowering for scalable masked deinterleaving loads (PR #154338)

[Cullen Rhodes via llvm-commits]

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@@ -27010,6 +27011,121 @@ performScalarToVectorCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
   return NVCAST;
 }
 
+static SDValue performVectorDeinterleaveCombine(
+    SDNode *N, TargetLowering::DAGCombinerInfo &DCI, SelectionDAG &DAG) {
+  unsigned NumParts = N->getNumOperands();
+  if (NumParts != 2 && NumParts != 4)
+    return SDValue();
+
+  EVT SubVecTy = N->getValueType(0);
+
+  // At the moment we're unlikely to see a fixed-width vector deinterleave as
+  // we usually generate shuffles instead.
+  unsigned MinNumElements = SubVecTy.getVectorMinNumElements();
+  if (!SubVecTy.isScalableVT() ||
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c-rhodes wrote:

>I also can't add tests for deinterleaving loads of vectors with i1 element types because we also fail during isel with the masked loads:
>
>LLVM ERROR: Cannot select: t24: nxv16i1,ch = masked_load<(load unknown-size, align 1)> t0, t23, undef:i64, t30, undef:nxv16i1

Apologies, I meant length 1 vector not vector of i1s. No worries 👍 



https://github.com/llvm/llvm-project/pull/154338