[llvm] [AMDGPU][LRO] LRO fix PHI same-BB filter; treat i8/i16 binops as profitable (PR #155800)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
index e4866405c..910da2be8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
@@ -128,7 +128,8 @@ public:
 
   bool isOpLegal(Instruction *I) {
     if (auto *Intr = dyn_cast<IntrinsicInst>(I))
-      return true; // FIXME: narrow to known native intrinsics (DOT/MFMA/tbuffer) or use TTI cost.
+      return true; // FIXME: narrow to known native intrinsics
+                   // (DOT/MFMA/tbuffer) or use TTI cost.
 
     // Any store is a profitable sink (prevents flip-flopping)
     if (isa<StoreInst>(I))
@@ -139,7 +140,8 @@ public:
       if (auto *VTy = dyn_cast<VectorType>(BO->getType())) {
         Type *Elt = VTy->getElementType();
         // Treat small-int vector binops as profitable when SDWA is available.
-        // We explicitly gate to 8/16-bit to avoid i1 vectors and keep behavior tight.
+        // We explicitly gate to 8/16-bit to avoid i1 vectors and keep behavior
+        // tight.
         if ((Elt->isIntegerTy(8) || (Elt->isIntegerTy(16)) && ST.hasSDWA())) {
           switch (BO->getOpcode()) {
           case Instruction::Add:
@@ -182,8 +184,8 @@ public:
 
       // Allow same-BB non-lookthrough users when the def is a PHI:
       // loop headers frequently consume the carried value in the header block
-      // (e.g. byte-wise vector binops). We *do* want to coerce across the backedge
-      // in that common case to enable packed i32 + SDWA lowering.
+      // (e.g. byte-wise vector binops). We *do* want to coerce across the
+      // backedge in that common case to enable packed i32 + SDWA lowering.
       if (CII->getParent() == II->getParent() && !IsLookThru(CII) &&
           !isa<PHINode>(II))
         continue;

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https://github.com/llvm/llvm-project/pull/155800