[clang] [llvm] [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for for MIPS RV64 P8700. (PR #155747)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 28 01:02:42 PDT 2025
================
@@ -99,89 +99,167 @@ class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
bits<5> rs2;
bits<5> rs1;
- let Inst{31-27} = rs3;
- let Inst{26-25} = imm7{6-5};
- let Inst{24-20} = rs2;
- let Inst{19-15} = rs1;
- let Inst{14-12} = 0b101;
- let Inst{11-9} = imm7{4-2};
- let Inst{8-7} = 0b01;
- let Inst{6-0} = OPC_CUSTOM_0.Value;
+ let Inst{31 - 27} = rs3;
+ let Inst{26 - 25} = imm7{6 - 5};
+ let Inst{24 - 20} = rs2;
+ let Inst{19 - 15} = rs1;
+ let Inst{14 - 12} = 0b101;
+ let Inst{11 - 9} = imm7{4 - 2};
+ let Inst{8 - 7} = 0b01;
+ let Inst{6 - 0} = OPC_CUSTOM_0.Value;
}
// Prefetch format.
-let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
-class Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
+let hasSideEffects = 0, mayLoad = 1,
+ mayStore = 1 in class
+ Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
bits<9> imm9;
bits<5> rs1;
bits<5> hint;
- let Inst{31-29} = 0b000;
- let Inst{28-20} = imm9;
- let Inst{19-15} = rs1;
- let Inst{14-12} = 0b000;
- let Inst{11-7} = hint;
- let Inst{6-0} = OPC_CUSTOM_0.Value;
+ let Inst{31 - 29} = 0b000;
+ let Inst{28 - 20} = imm9;
+ let Inst{19 - 15} = rs1;
+ let Inst{14 - 12} = 0b000;
+ let Inst{11 - 7} = hint;
+ let Inst{6 - 0} = OPC_CUSTOM_0.Value;
+}
+
+// MIPS Ext Insns
+let hasSideEffects = 1, mayLoad = 0,
+ mayStore = 0 in class MIPSExtInst_ri<bits<6> shimm5, string opcodestr>
+ : RVInstIShift<0b00000, 0b001, OPC_OP_IMM, (outs), (ins), opcodestr, ""> {
+ let shamt = shimm5;
+ let rd = 0;
+ let rs1 = 0;
}
//===----------------------------------------------------------------------===//
// MIPS extensions
//===----------------------------------------------------------------------===//
-let Predicates = [HasVendorXMIPSCBOP] ,DecoderNamespace = "Xmipscbop" in {
- def MIPS_PREF : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
- "mips.pref", "$hint, ${imm9}(${rs1})">,
- Sched<[]>;
+let Predicates = [HasVendorXMIPSCBOP], DecoderNamespace = "XMIPS" in {
+ def MIPS_PREF : Mips_prefetch_ri<(outs),
+ (ins GPR
----------------
ukalappa-mips wrote:
same ...anyway ..will rewrite accordingly ..
https://github.com/llvm/llvm-project/pull/155747
More information about the llvm-commits
mailing list