[llvm] [GISel] Combine shift + trunc + shift pattern (PR #155583)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 28 01:00:51 PDT 2025
================
@@ -2094,6 +2094,60 @@ bool CombinerHelper::matchCommuteShift(MachineInstr &MI,
return true;
}
+bool CombinerHelper::matchShiftOfTruncOfShift(
+ MachineInstr &MI, ShiftOfTruncOfShift &MatchInfo) const {
+ unsigned ShiftOpcode = MI.getOpcode();
+ assert(ShiftOpcode == TargetOpcode::G_LSHR ||
+ ShiftOpcode == TargetOpcode::G_ASHR);
+
+ Register N0 = MI.getOperand(1).getReg();
+ Register N1 = MI.getOperand(2).getReg();
+ unsigned OpSizeInBits = MRI.getType(N0).getScalarSizeInBits();
+
+ APInt N1C;
+ Register InnerShift;
+ if (!mi_match(N1, MRI, m_ICstOrSplat(N1C)) ||
+ !mi_match(N0, MRI, m_GTrunc(m_Reg(InnerShift))))
+ return false;
+
+ auto *InnerMI = MRI.getVRegDef(InnerShift);
+ if (InnerMI->getOpcode() != ShiftOpcode)
+ return false;
+
+ APInt N001C;
+ auto N001 = InnerMI->getOperand(2).getReg();
+ if (!mi_match(N001, MRI, m_ICstOrSplat(N001C)))
+ return false;
+
+ uint64_t c1 = N001C.getZExtValue();
+ uint64_t c2 = N1C.getZExtValue();
----------------
davemgreen wrote:
C1, C2.
Be careful of getZExtValue for values larger than 64bits.
https://github.com/llvm/llvm-project/pull/155583
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