[llvm] [SPARC] Weaken emitted barriers for atomic ops (PR #154950)

[Matt Arsenault via llvm-commits]

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@@ -261,6 +263,26 @@ void SparcAsmPrinter::LowerGETPCXAndEmitMCInsts(const MachineInstr *MI,
   EmitADD(*OutStreamer, MCRegOP, RegO7, MCRegOP, STI);
 }
 
+void SparcAsmPrinter::LowerV8Bar(const MachineInstr *MI,
+                                 const MCSubtargetInfo &STI) {
+  assert(!STI.hasFeature(Sparc::FeatureV9) &&
+         "V8BAR should not be emitted on V9 processors!");
+
+  MCInst STBARInst;
+  MCInst LDSTUBInst;
+
+  // Emit stbar; ldstub [%sp-1], %g0
+  // The sequence acts as a full barrier on V8 systems.
+  STBARInst.setOpcode(SP::STBAR);
+  LDSTUBInst.setOpcode(SP::LDSTUBri);
+  LDSTUBInst.addOperand(MCOperand::createReg(SP::G0));
+  LDSTUBInst.addOperand(MCOperand::createReg(SP::O6));
+  LDSTUBInst.addOperand(MCOperand::createImm(-1));
+
+  OutStreamer->emitInstruction(STBARInst, STI);
+  OutStreamer->emitInstruction(LDSTUBInst, STI);
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arsenm wrote:

(that's assuming these actually need to be kept immediately sequential) 

https://github.com/llvm/llvm-project/pull/154950