[llvm] [AArch64][SDAG] Lower f16->s16 FP_TO_INT_SAT to *v1f16 (PR #154822)

[Kajetan Puchalski via llvm-commits]

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@@ -2536,6 +2537,24 @@ void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
   ReplaceNode(N, St);
 }
 
+// Select f16 -> i16 conversions
+// Since i16 is an illegal type, we return the converted bit pattern in a f32
+// which can then be bitcast to i32 and truncated as needed.
+void AArch64DAGToDAGISel::SelectFCVT_FPTOINT_Half(SDNode *N, unsigned int Opc) {
+  SDLoc DL(N);
+  SDValue SrcVal = N->getOperand(0);
+  SDNode *Cvt = CurDAG->getMachineNode(Opc, DL, MVT::f16, SrcVal);
+  SDValue Sign = CurDAG->getTargetConstant(-1, DL, MVT::i64);
+  SDValue Hsub = CurDAG->getTargetConstant(AArch64::hsub, DL, MVT::i32);
+  SDNode *SubregToReg = CurDAG->getMachineNode(
+      TargetOpcode::SUBREG_TO_REG, DL, MVT::v8f16, Sign, SDValue(Cvt, 0), Hsub);
+  SDValue Ssub = CurDAG->getTargetConstant(AArch64::ssub, DL, MVT::i32);
+  SDNode *Extract =
+      CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f32,
+                             SDValue(SubregToReg, 0), Ssub);
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mrkajetanp wrote:

Do you have any comparable examples for what that would look like? I was under the impression that TableGen patterns are supposed to output just one node, hence I wrote this in C++. I am however new to ISel so it's pretty likely I'm not aware of some things.

https://github.com/llvm/llvm-project/pull/154822