[llvm] [Intrinsics][AArch64] Add intrinsics for masking off aliasing vector lanes (PR #117007)

[Sam Tebbs via llvm-commits]

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@@ -24184,18 +24184,10 @@ This is an overloaded intrinsic.
 Overview:
 """""""""
 
-Given a scalar store to %ptrA, followed by a scalar load from %ptrB, this
-instruction generates a mask where an active lane indicates that there is no
-read-after-write hazard for this lane and that this lane does not introduce any
-new store-to-load forwarding hazard.
-
-A read-after-write hazard occurs when a read-after-write sequence for a given
-lane in a vector ends up being executed as a write-after-read sequence due to
-the aliasing of pointers.
-
-Note that the case where (ptrB - ptrA) < 0 does not result in any
-read-after-write hazards, but may introduce new store-to-load-forwarding stalls
-where both the store and load partially access the same addresses.
+Given a vector store to %ptrA, followed by a vector load from %ptrB, this
+instruction generates a mask where an active lane indicates that the accesses
+can be made safely without a lane being read from before being stored to.
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SamTebbs33 wrote:

I like that wording, thanks. Done.

https://github.com/llvm/llvm-project/pull/117007