[llvm] [AArch64] Update cost model for extracting halves from 128+ bit vectors (PR #155601)

[Paul Walker via llvm-commits]

=?utf-8?q?Gaëtan?= Bossu <gaetan.bossu at arm.com>
Message-ID:
In-Reply-To: <llvm.org/llvm/llvm-project/pull/155601 at github.com>


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@@ -96,8 +102,129 @@ define void @extract_half() {
   ret void
 }
 
-define void @extract_qtr() {
-; CHECK-LABEL: 'extract_qtr'
+; Similar as above, but for a 256-bit SVE core.
+; Vectors smaller than 256-bit aren't tested again.
+define void @extract_half_vscale2() vscale_range(2,2) {
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paulwalker-arm wrote:

`vscale_range` can change the list of legal types. In this instance `vscale_range(2,2)` means 256-bit vector types are legal, which has the effect of changing the result of `LT = getTypeLegalizationCost(...)` that is used when computing instruction costs.

https://github.com/llvm/llvm-project/pull/155601