[llvm] 024618b - [X86] canCreateUndefOrPoisonForTargetNode - add SSE bit logic + VPTERNLOG handling (#155600)

[via llvm-commits]

Author: Simon Pilgrim
Date: 2025-08-27T13:59:31+01:00
New Revision: 024618b7a0068b40810b72096523e29076af7160

URL: https://github.com/llvm/llvm-project/commit/024618b7a0068b40810b72096523e29076af7160
DIFF: https://github.com/llvm/llvm-project/commit/024618b7a0068b40810b72096523e29076af7160.diff

LOG: [X86] canCreateUndefOrPoisonForTargetNode - add SSE bit logic + VPTERNLOG handling (#155600)

Basic bitlogic operations don't create undef/poison.

Its proving really annoying to create proper test coverage for these
specific opcodes as they tend to appear in later stages - their presence
does help in some upcoming patches (e.g. #152107) and I'd prefer to get
them committed early.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 9a3e79569df50..ab21cf534b304 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -45150,6 +45150,14 @@ bool X86TargetLowering::canCreateUndefOrPoisonForTargetNode(
     bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const {
 
   switch (Op.getOpcode()) {
+  // SSE bit logic.
+  case X86ISD::FAND:
+  case X86ISD::FOR:
+  case X86ISD::FXOR:
+  case X86ISD::FANDN:
+  case X86ISD::ANDNP:
+  case X86ISD::VPTERNLOG:
+    return false;
   // SSE vector insert/extracts use modulo indices.
   case X86ISD::PINSRB:
   case X86ISD::PINSRW: