[llvm] [DAGCombiner] add fold (xor (smin(x, C), C)) and fold (xor (smax(x, C), C)) (PR #155141)

[Simon Pilgrim via llvm-commits]

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@@ -10086,6 +10086,51 @@ SDValue DAGCombiner::visitXOR(SDNode *N) {
   if (SDValue Combined = combineCarryDiamond(DAG, TLI, N0, N1, N))
     return Combined;
 
+  // fold (xor (smin(x, C), C)) -> select (x < C), xor(x, C), 0
+  // fold (xor (smax(x, C), C)) -> select (x > C), xor(x, C), 0
+  // fold (xor (umin(x, C), C)) -> select (x < C), xor(x, C), 0
+  // fold (xor (umax(x, C), C)) -> select (x > C), xor(x, C), 0
+  SDValue Op0, Op1;
+  if ((sd_match(N0, m_OneUse(m_AnyOf(m_SMin(m_Value(Op0), m_Value(Op1)),
+                                     m_SMax(m_Value(Op0), m_Value(Op1)),
+                                     m_UMin(m_Value(Op0), m_Value(Op1)),
+                                     m_UMax(m_Value(Op0), m_Value(Op1))))))) {
+
+    if (Op1 == N1) {
+      if (isa<ConstantSDNode>(N1) ||
+          ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
+        // For vectors, only optimize when the constant is zero or all-ones to
+        // avoid generating more instructions
+        if (VT.isVector()) {
+          ConstantSDNode *N1C = isConstOrConstSplat(N1);
+          if (!N1C || (!N1C->isZero() && !N1C->isAllOnes()))
+            return SDValue();
+        }
+
+        EVT CCVT = getSetCCResultType(VT);
+        ISD::CondCode CC;
+        switch (N0.getOpcode()) {
+        case ISD::SMIN:
+          CC = ISD::SETLT;
+          break;
+        case ISD::SMAX:
+          CC = ISD::SETGT;
+          break;
+        case ISD::UMIN:
+          CC = ISD::SETULT;
+          break;
+        case ISD::UMAX:
+          CC = ISD::SETUGT;
+          break;
+        }
+        SDValue Cmp = DAG.getSetCC(SDLoc(N), CCVT, Op0, N1, CC);
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RKSimon wrote:

visitXOR already has DL that can be used instead of all these repeated SDLoc(N) calls

https://github.com/llvm/llvm-project/pull/155141