[llvm] [AArch64][SME] Address post-review comments on the MachineSMEABIPass (NFC) (PR #155588)
Benjamin Maxwell via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 27 03:14:56 PDT 2025
https://github.com/MacDue created https://github.com/llvm/llvm-project/pull/155588
None
>From 86ecd0873320c155d0982fbf6eba5d650566c77c Mon Sep 17 00:00:00 2001
From: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: Wed, 27 Aug 2025 10:12:38 +0000
Subject: [PATCH] [AArch64][SME] Address post-review comments on the
MachineSMEABIPass (NFC)
---
llvm/lib/Target/AArch64/MachineSMEABIPass.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
index b58dfdf32e4ab..5dfaa891193cf 100644
--- a/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
+++ b/llvm/lib/Target/AArch64/MachineSMEABIPass.cpp
@@ -139,8 +139,8 @@ StringRef getZAStateString(ZAState State) {
#undef MAKE_CASE
}
-static bool isZAorZT0RegOp(const TargetRegisterInfo &TRI,
- const MachineOperand &MO) {
+static bool isZAorZTRegOp(const TargetRegisterInfo &TRI,
+ const MachineOperand &MO) {
if (!MO.isReg() || !MO.getReg().isPhysical())
return false;
return any_of(TRI.subregs_inclusive(MO.getReg()), [](const MCPhysReg &SR) {
@@ -166,7 +166,7 @@ getZAStateBeforeInst(const TargetRegisterInfo &TRI, MachineInstr &MI,
return {ZAOffAtReturn ? ZAState::OFF : ZAState::ACTIVE, InsertPt};
for (auto &MO : MI.operands()) {
- if (isZAorZT0RegOp(TRI, MO))
+ if (isZAorZTRegOp(TRI, MO))
return {ZAState::ACTIVE, InsertPt};
}
@@ -266,7 +266,7 @@ void MachineSMEABI::collectNeededZAStates(SMEAttrs SMEFnAttrs) {
State.Blocks.resize(MF->getNumBlockIDs());
for (MachineBasicBlock &MBB : *MF) {
BlockInfo &Block = State.Blocks[MBB.getNumber()];
- if (&MBB == &MF->front()) {
+ if (MBB.isEntryBlock()) {
// Entry block:
Block.FixedEntryState = SMEFnAttrs.hasPrivateZAInterface()
? ZAState::CALLER_DORMANT
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