[llvm] [llvm-exegesis] [AArch64] Resolving "not all operands are initialized by snippet generator" (PR #142529)

[David Green via llvm-commits]

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@@ -152,6 +156,48 @@ class ExegesisAArch64Target : public ExegesisTarget {
   }
 };
 
+Error ExegesisAArch64Target::randomizeTargetMCOperand(
+    const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
+    const BitVector &ForbiddenRegs) const {
+  const Operand &Op = Instr.getPrimaryOperand(Var);
+  const auto OperandType = Op.getExplicitOperandInfo().OperandType;
+  //  FIXME: Implement opcode-specific immediate value handling for system
+  //  instructions:
+  //   - MRS/MSR: Use valid system register encodings (e.g., NZCV, FPCR, FPSR)
+  //   - MSRpstatesvcrImm1: Use valid PSTATE field encodings (e.g., SPSel,
+  //   DAIFSet)
+  //   - SYSLxt/SYSxt: Use valid system instruction encodings with proper
+  //   CRn/CRm/op values
+  //   - UDF: Use valid undefined instruction immediate ranges (0-65535)
+  //   Currently defaulting to immediate value 0, which may cause invalid
+  //   encodings or unreliable benchmark results for these system-level
+  //   instructions.
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davemgreen wrote:

I'm not sure if these system level instructions are easy to test (or very interesting). Some of the MRS/MSR variants would be fine, but they might be worth treating as special cases.

https://github.com/llvm/llvm-project/pull/142529