[llvm] [RISCV] Improve some debug messages from RISCVVLOptimizer. NFC (PR #155524)

via llvm-commits llvm-commits at lists.llvm.org
Tue Aug 26 17:09:28 PDT 2025


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git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
index 21423a488..01aef86ee 100644
--- a/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
@@ -1306,7 +1306,8 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
   // TODO: Use a better approach than a white-list, such as adding
   // properties to instructions using something like TSFlags.
   if (!isSupportedInstr(MI)) {
-    LLVM_DEBUG(dbgs() << "Not a candidate due to unsupported instruction: " << MI);
+    LLVM_DEBUG(dbgs() << "Not a candidate due to unsupported instruction: "
+                      << MI);
     return false;
   }
 
@@ -1487,8 +1488,7 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI) const {
   }
   const MachineInstr *VLMI = MRI->getVRegDef(CommonVL->getReg());
   if (!MDT->dominates(VLMI, &MI)) {
-    LLVM_DEBUG(
-        dbgs() << "  Abort due to VL not dominating.\n");
+    LLVM_DEBUG(dbgs() << "  Abort due to VL not dominating.\n");
     return false;
   }
   LLVM_DEBUG(

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https://github.com/llvm/llvm-project/pull/155524


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