[llvm] [AArch64][SDAG] Lower f16->s16 FP_TO_INT_SAT to *v1f16 (PR #154822)

[Eli Friedman via llvm-commits]

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@@ -2536,6 +2537,25 @@ void AArch64DAGToDAGISel::SelectPostStoreLane(SDNode *N, unsigned NumVecs,
   ReplaceNode(N, St);
 }
 
+// Select f16 -> i16 conversions
+// Since i16 is an illegal type, they need to return an i32 result
+void AArch64DAGToDAGISel::SelectFCVT_FPTOINT_Half(SDNode *N, unsigned int Opc) {
+  SDLoc DL(N);
+  SDValue SrcVal = N->getOperand(0);
+  SDNode *Cvt = CurDAG->getMachineNode(Opc, DL, MVT::f16, SrcVal);
+  SDValue Sign = CurDAG->getTargetConstant(-1, DL, MVT::i64);
+  SDValue Hsub = CurDAG->getTargetConstant(AArch64::hsub, DL, MVT::i32);
+  SDNode *SubregToReg = CurDAG->getMachineNode(
+      TargetOpcode::SUBREG_TO_REG, DL, MVT::v8f16, Sign, SDValue(Cvt, 0), Hsub);
+  SDValue Ssub = CurDAG->getTargetConstant(AArch64::ssub, DL, MVT::i32);
+  SDNode *Extract =
+      CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL, MVT::f32,
+                             SDValue(SubregToReg, 0), Ssub);
+  SDNode *Result = CurDAG->getMachineNode(AArch64::FMOVSWr, DL, MVT::i32,
+                                          SDValue(Extract, 0));
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efriedma-quic wrote:

Instead of making FCVTZS_HALF return an i32, and using AArch64::FMOVSWr to move the result into an integer register, can we make it return an f32, and then "ISD::BITCAST" that to i32 in AArch64TargetLowering::LowerFP_TO_INT_SAT?  Separating the register move allows optimizing subsequent operations, like if we insert the result of the conversion into a vector.

(This is what I mentioned on #154344.)

https://github.com/llvm/llvm-project/pull/154822