[llvm] [NFC][MC][XCore] Eliminate forward decls by rearranging functions (PR #155456)

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github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. :warning:

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<summary>
You can test this locally with the following command:
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``````````bash
git-clang-format --diff HEAD~1 HEAD --extensions cpp -- llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
``````````

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<details>
<summary>
View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
index 1002d1c8d..f2a6723b2 100644
--- a/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
+++ b/llvm/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
@@ -204,7 +204,7 @@ static DecodeStatus DecodeL3RInstruction(MCInst &Inst, unsigned Insn,
                                          const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S =
-    Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
+      Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
@@ -218,7 +218,7 @@ static DecodeStatus DecodeL3RSrcDstInstruction(MCInst &Inst, unsigned Insn,
                                                const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S =
-  Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
+      Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
@@ -233,7 +233,7 @@ static DecodeStatus DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn,
                                            const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S =
-  Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
+      Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
@@ -247,7 +247,7 @@ static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
                                                const MCDisassembler *Decoder) {
   unsigned Op1, Op2, Op3;
   DecodeStatus S =
-  Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
+      Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3);
   if (S == MCDisassembler::Success) {
     DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
     DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
@@ -256,7 +256,6 @@ static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn,
   return S;
 }
 
-
 static DecodeStatus Decode2OpInstructionFail(MCInst &Inst, unsigned Insn,
                                              uint64_t Address,
                                              const MCDisassembler *Decoder) {

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https://github.com/llvm/llvm-project/pull/155456