[llvm] [RISCV] Use slideup to lower build_vector when its last operand is an extraction (PR #154450)

[Philip Reames via llvm-commits]

https://github.com/preames commented:

So, high level question on profitability.  The reason we prefer slidedown is that slideup has a register constraint which forces the use of two registers through the build sequence.  Particularly at high LMUL, doubling the register pressure is really expensive.  We do cap at m2 today, so maybe that's not too bad a problem?

For the motivating sequence, have you considered using a normal slidedown sequence, and then a single vslideup (not slide1up) from the source register into the last destination?  I think you end up with one extra slide1down (to put the other elements in the right spot), but this might be cheaper overall?

https://github.com/llvm/llvm-project/pull/154450