[llvm] [AMDGPU] Extending wave reduction intrinsics for `i64` types - 1 (PR #150169)

[via llvm-commits]

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@@ -5313,6 +5339,11 @@ static MachineBasicBlock *lowerWaveReduce(MachineInstr &MI,
     // so that we will get the next active lane for next iteration.
     MachineBasicBlock::iterator I = BB.end();
     Register SrcReg = MI.getOperand(1).getReg();
+    bool is32BitOpc = (Opc == AMDGPU::S_MIN_U32 || Opc == AMDGPU::S_MIN_I32 ||
+                       Opc == AMDGPU::S_MAX_U32 || Opc == AMDGPU::S_MAX_I32 ||
+                       Opc == AMDGPU::S_ADD_I32 || Opc == AMDGPU::S_SUB_I32 ||
+                       Opc == AMDGPU::S_AND_B32 || Opc == AMDGPU::S_OR_B32 ||
+                       Opc == AMDGPU::S_XOR_B32);
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easyonaadit wrote:

Extracted this into a helper function instead.

https://github.com/llvm/llvm-project/pull/150169