[llvm] [RISCV] Loosen the requirement of shadow stack codegen to Zimop (PR #152251)

[Ming-Yi Lai via llvm-commits]

================
@@ -124,7 +130,12 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
 
   const RISCVInstrInfo *TII = STI.getInstrInfo();
   if (HasHWShadowStack) {
-    BuildMI(MBB, MI, DL, TII->get(RISCV::SSPUSH)).addReg(RAReg);
+    if (STI.hasStdExtZcmop()) {
+      static_assert(RAReg == RISCV::X1);
----------------
mylai-mtk wrote:

```suggestion
      static_assert(RAReg == RISCV::X1, "C.SSPUSH only accepts X1");
```

https://github.com/llvm/llvm-project/pull/152251