[llvm] [AMDGPU] Implement IR expansion for frem instruction (PR #130988)

[Frederik Harwath via llvm-commits]

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@@ -2393,21 +2393,6 @@ SDValue AMDGPUTargetLowering::LowerSDIVREM(SDValue Op,
   return DAG.getMergeValues(Res, DL);
 }
 
-// (frem x, y) -> (fma (fneg (ftrunc (fdiv x, y))), y, x)
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frederik-h wrote:

@arsenm I have now added this expansion for the case in which the fast math flags contain afn. This way, we get essentially the same IR as before for that case except that I do not propagate the fast math flags to the instructions in the expansion because we had observed an undesirable precision loss with this in the past; you can compare the expansion with the lowering in this [commit](https://github.com/frederik-h/llvm-project/commit/3729e4ce9c6df04d473a5115e8bdc91c9aaab094#diffb703500b1e78af4873a53b1305203c0426ee5893d9dae8fc786d9491beec4bd8L287-R287) in a dev branch of mine which tried to provide a workaround for the precision problem.

https://github.com/llvm/llvm-project/pull/130988