[llvm] [RISCV] Loosen the requirement of shadow stack codegen to Zimop (PR #152251)

[Ming-Yi Lai via llvm-commits]

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@@ -107,7 +107,7 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
                             const DebugLoc &DL) {
   const auto &STI = MF.getSubtarget<RISCVSubtarget>();
   bool HasHWShadowStack = MF.getFunction().hasFnAttribute("hw-shadow-stack") &&
-                          STI.hasStdExtZicfiss();
+                          STI.hasStdExtZimop();
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mylai-mtk wrote:

Hi, generally I do agree that these Zicfiss insns would not be useful if their surrounding insn choreography is not wholly available. But hey, our purpose here is to aggressively sneak in Zicfiss protection, even if the feature is known to be unavailable at compile time, so I guess the assumption that these insns would be useless without the complete ISA support is a bit... contradictory to our mindset here. 

Anyway, your current code is correct and suitable, but I still wish you could uhhh... do something to justify why Zcmop is not checked at this line despite using it down below to emit SSPUSH, since with the above mindset, we're aggressively sneaking in unsupported insns that are known to be harmless, so why not enable hardware shadow stack if only Zcmop is available?

https://github.com/llvm/llvm-project/pull/152251