[llvm] [RISCV] Loosen the requirement of shadow stack codegen to Zimop (PR #152251)

[Ming-Yi Lai via llvm-commits]

================
@@ -62,6 +62,21 @@ defm SSAMOSWAP_W  : AMO_rr_aq_rl<0b01001, 0b010, "ssamoswap.w">;
 let Predicates = [HasStdExtZicfiss, IsRV64] in
 defm SSAMOSWAP_D  : AMO_rr_aq_rl<0b01001, 0b011, "ssamoswap.d">;
 
+let Predicates = [HasStdExtZimop] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def PseudoMOP_SSPUSH : Pseudo<(outs), (ins GPRX1X5:$rs2), []>,
+    PseudoInstExpansion<(MOPRR7 X0, X0, GPR:$rs2)>;
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+def PseudoMOP_SSPOPCHK : Pseudo<(outs), (ins GPRX1X5:$rs1), []>,
+    PseudoInstExpansion<(MOPR28 X0, GPR:$rs1)>;
+} // Predicates = [HasStdExtZimop]
+
+let Predicates = [HasStdExtZcmop] in {
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+def PseudoMOP_C_SSPUSH : Pseudo<(outs), (ins GPRX1:$ra), []>,
----------------
mylai-mtk wrote:

Since C.SSPUSH does not take non-X1 registers, I think it's better to capture the X1 register as an implicit use and remove the possibility of supplying a non-X1 register.

https://github.com/llvm/llvm-project/pull/152251