[llvm] [AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed. (PR #154769)
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 21 07:06:46 PDT 2025
https://github.com/kosarev created https://github.com/llvm/llvm-project/pull/154769
Saves around 125-210 MB of compilation memory usage per source for roughly one third of our backend sources, ~60 MB on average.
>From 18eaf1f776b95558e658928418f6fbac82d57924 Mon Sep 17 00:00:00 2001
From: Ivan Kosarev <ivan.kosarev at amd.com>
Date: Mon, 18 Aug 2025 13:44:22 +0100
Subject: [PATCH] [AMDGPU][NFC] Only include CodeGenPassBuilder.h where needed.
Saves around 125-210 MB of compilation memory usage per source for
roughly one third of our backend sources, ~60 MB on average.
---
.../Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 2 +
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 1 +
.../AMDGPU/AMDGPULateCodeGenPrepare.cpp | 1 +
.../AMDGPU/AMDGPULowerBufferFatPointers.cpp | 2 +
.../AMDGPU/AMDGPULowerModuleLDSPass.cpp | 2 +
.../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 39 +++++++++++++++++++
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 39 -------------------
llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 1 +
llvm/lib/Target/AMDGPU/R600TargetMachine.cpp | 16 ++++++++
llvm/lib/Target/AMDGPU/R600TargetMachine.h | 15 -------
.../Target/AMDGPU/SIAnnotateControlFlow.cpp | 2 +
llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp | 4 ++
.../Target/AMDGPU/SILateBranchLowering.cpp | 1 +
llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 1 +
.../Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp | 1 +
.../Target/AMDGPU/SIPreAllocateWWMRegs.cpp | 1 +
llvm/unittests/Target/AMDGPU/CSETest.cpp | 1 +
17 files changed, 75 insertions(+), 54 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
index a9278c1dc3a6a..24bef82464495 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
@@ -18,6 +18,7 @@
#include "llvm/Analysis/AssumptionCache.h"
#include "llvm/Analysis/ConstantFolding.h"
#include "llvm/Analysis/TargetLibraryInfo.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/UniformityAnalysis.h"
#include "llvm/Analysis/ValueTracking.h"
#include "llvm/CodeGen/TargetPassConfig.h"
@@ -26,6 +27,7 @@
#include "llvm/IR/InstVisitor.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/PatternMatch.h"
+#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Support/KnownFPClass.h"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 04c4d000547a4..b80e43b27129b 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -27,6 +27,7 @@
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/CodeGen/SelectionDAGNodes.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
+#include "llvm/InitializePasses.h"
#include "llvm/Support/ErrorHandling.h"
#ifdef EXPENSIVE_CHECKS
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
index 56113e6dd9f97..38718c43a61dd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
@@ -21,6 +21,7 @@
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InstVisitor.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
+#include "llvm/InitializePasses.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/KnownBits.h"
#include "llvm/Transforms/Utils/Local.h"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
index 139cad60ebcb2..7dc1ec07cf0f9 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerBufferFatPointers.cpp
@@ -225,6 +225,7 @@
#include "llvm/ADT/SetOperations.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/Analysis/InstSimplifyFolder.h"
+#include "llvm/Analysis/TargetTransformInfo.h"
#include "llvm/Analysis/Utils/Local.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/AttributeMask.h"
@@ -243,6 +244,7 @@
#include "llvm/IR/PatternMatch.h"
#include "llvm/IR/ReplaceConstant.h"
#include "llvm/IR/ValueHandle.h"
+#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/Support/AMDGPUAddrSpace.h"
#include "llvm/Support/Alignment.h"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp b/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
index 93f9c7d7fb176..f01d5f6726822 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULowerModuleLDSPass.cpp
@@ -190,12 +190,14 @@
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/Dominators.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/InlineAsm.h"
#include "llvm/IR/Instructions.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/MDBuilder.h"
#include "llvm/IR/ReplaceConstant.h"
+#include "llvm/InitializePasses.h"
#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index e393aa1987744..e969f9ec88899 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -90,6 +90,7 @@
#include "llvm/IR/PatternMatch.h"
#include "llvm/InitializePasses.h"
#include "llvm/MC/TargetRegistry.h"
+#include "llvm/Passes/CodeGenPassBuilder.h"
#include "llvm/Passes/PassBuilder.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/FormatVariadic.h"
@@ -125,6 +126,44 @@ using namespace llvm;
using namespace llvm::PatternMatch;
namespace {
+//===----------------------------------------------------------------------===//
+// AMDGPU CodeGen Pass Builder interface.
+//===----------------------------------------------------------------------===//
+
+class AMDGPUCodeGenPassBuilder
+ : public CodeGenPassBuilder<AMDGPUCodeGenPassBuilder, GCNTargetMachine> {
+ using Base = CodeGenPassBuilder<AMDGPUCodeGenPassBuilder, GCNTargetMachine>;
+
+public:
+ AMDGPUCodeGenPassBuilder(GCNTargetMachine &TM,
+ const CGPassBuilderOption &Opts,
+ PassInstrumentationCallbacks *PIC);
+
+ void addIRPasses(AddIRPass &) const;
+ void addCodeGenPrepare(AddIRPass &) const;
+ void addPreISel(AddIRPass &addPass) const;
+ void addILPOpts(AddMachinePass &) const;
+ void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const;
+ Error addInstSelector(AddMachinePass &) const;
+ void addPreRewrite(AddMachinePass &) const;
+ void addMachineSSAOptimization(AddMachinePass &) const;
+ void addPostRegAlloc(AddMachinePass &) const;
+ void addPreEmitPass(AddMachinePass &) const;
+ void addPreEmitRegAlloc(AddMachinePass &) const;
+ Error addRegAssignmentOptimized(AddMachinePass &) const;
+ void addPreRegAlloc(AddMachinePass &) const;
+ void addOptimizedRegAlloc(AddMachinePass &) const;
+ void addPreSched2(AddMachinePass &) const;
+
+ /// Check if a pass is enabled given \p Opt option. The option always
+ /// overrides defaults if explicitly used. Otherwise its default will be used
+ /// given that a pass shall work at an optimization \p Level minimum.
+ bool isPassEnabled(const cl::opt<bool> &Opt,
+ CodeGenOptLevel Level = CodeGenOptLevel::Default) const;
+ void addEarlyCSEOrGVNPass(AddIRPass &) const;
+ void addStraightLineScalarOptimizationPasses(AddIRPass &) const;
+};
+
class SGPRRegisterRegAlloc : public RegisterRegAllocBase<SGPRRegisterRegAlloc> {
public:
SGPRRegisterRegAlloc(const char *N, const char *D, FunctionPassCtor C)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index e0f1296ddded8..06a3047196b8a 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -18,7 +18,6 @@
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/MC/MCStreamer.h"
-#include "llvm/Passes/CodeGenPassBuilder.h"
#include <optional>
#include <utility>
@@ -158,44 +157,6 @@ class AMDGPUPassConfig : public TargetPassConfig {
}
};
-//===----------------------------------------------------------------------===//
-// AMDGPU CodeGen Pass Builder interface.
-//===----------------------------------------------------------------------===//
-
-class AMDGPUCodeGenPassBuilder
- : public CodeGenPassBuilder<AMDGPUCodeGenPassBuilder, GCNTargetMachine> {
- using Base = CodeGenPassBuilder<AMDGPUCodeGenPassBuilder, GCNTargetMachine>;
-
-public:
- AMDGPUCodeGenPassBuilder(GCNTargetMachine &TM,
- const CGPassBuilderOption &Opts,
- PassInstrumentationCallbacks *PIC);
-
- void addIRPasses(AddIRPass &) const;
- void addCodeGenPrepare(AddIRPass &) const;
- void addPreISel(AddIRPass &addPass) const;
- void addILPOpts(AddMachinePass &) const;
- void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const;
- Error addInstSelector(AddMachinePass &) const;
- void addPreRewrite(AddMachinePass &) const;
- void addMachineSSAOptimization(AddMachinePass &) const;
- void addPostRegAlloc(AddMachinePass &) const;
- void addPreEmitPass(AddMachinePass &) const;
- void addPreEmitRegAlloc(AddMachinePass &) const;
- Error addRegAssignmentOptimized(AddMachinePass &) const;
- void addPreRegAlloc(AddMachinePass &) const;
- void addOptimizedRegAlloc(AddMachinePass &) const;
- void addPreSched2(AddMachinePass &) const;
-
- /// Check if a pass is enabled given \p Opt option. The option always
- /// overrides defaults if explicitly used. Otherwise its default will be used
- /// given that a pass shall work at an optimization \p Level minimum.
- bool isPassEnabled(const cl::opt<bool> &Opt,
- CodeGenOptLevel Level = CodeGenOptLevel::Default) const;
- void addEarlyCSEOrGVNPass(AddIRPass &) const;
- void addStraightLineScalarOptimizationPasses(AddIRPass &) const;
-};
-
} // end namespace llvm
#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUTARGETMACHINE_H
diff --git a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
index 3c8bfa629ed3d..2aa54c920a046 100644
--- a/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
#include "llvm/IR/IntrinsicsR600.h"
+#include "llvm/Passes/CodeGenPassBuilder.h"
using namespace llvm;
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
index eff5b0aad0248..c20487ebd8fc9 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
@@ -19,6 +19,7 @@
#include "R600MachineFunctionInfo.h"
#include "R600MachineScheduler.h"
#include "R600TargetTransformInfo.h"
+#include "llvm/Passes/CodeGenPassBuilder.h"
#include "llvm/Transforms/Scalar.h"
#include <optional>
@@ -46,6 +47,21 @@ static MachineSchedRegistry R600SchedRegistry("r600",
"Run R600's custom scheduler",
createR600MachineScheduler);
+//===----------------------------------------------------------------------===//
+// R600 CodeGen Pass Builder interface.
+//===----------------------------------------------------------------------===//
+
+class R600CodeGenPassBuilder
+ : public CodeGenPassBuilder<R600CodeGenPassBuilder, R600TargetMachine> {
+public:
+ R600CodeGenPassBuilder(R600TargetMachine &TM, const CGPassBuilderOption &Opts,
+ PassInstrumentationCallbacks *PIC);
+
+ void addPreISel(AddIRPass &addPass) const;
+ void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const;
+ Error addInstSelector(AddMachinePass &) const;
+};
+
//===----------------------------------------------------------------------===//
// R600 Target Machine (R600 -> Cayman)
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AMDGPU/R600TargetMachine.h b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
index eb4cb91cb704d..7985ef136cead 100644
--- a/llvm/lib/Target/AMDGPU/R600TargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/R600TargetMachine.h
@@ -57,21 +57,6 @@ class R600TargetMachine final : public AMDGPUTargetMachine {
createMachineScheduler(MachineSchedContext *C) const override;
};
-//===----------------------------------------------------------------------===//
-// R600 CodeGen Pass Builder interface.
-//===----------------------------------------------------------------------===//
-
-class R600CodeGenPassBuilder
- : public CodeGenPassBuilder<R600CodeGenPassBuilder, R600TargetMachine> {
-public:
- R600CodeGenPassBuilder(R600TargetMachine &TM, const CGPassBuilderOption &Opts,
- PassInstrumentationCallbacks *PIC);
-
- void addPreISel(AddIRPass &addPass) const;
- void addAsmPrinter(AddMachinePass &, CreateMCStreamer) const;
- Error addInstSelector(AddMachinePass &) const;
-};
-
} // end namespace llvm
#endif // LLVM_LIB_TARGET_AMDGPU_R600TARGETMACHINE_H
diff --git a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
index 3be7e5a16c825..f041e94c9161d 100644
--- a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
@@ -16,12 +16,14 @@
#include "GCNSubtarget.h"
#include "llvm/Analysis/LoopInfo.h"
#include "llvm/Analysis/UniformityAnalysis.h"
+#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/TargetPassConfig.h"
#include "llvm/IR/BasicBlock.h"
#include "llvm/IR/Constants.h"
#include "llvm/IR/Dominators.h"
#include "llvm/IR/IRBuilder.h"
#include "llvm/IR/IntrinsicsAMDGPU.h"
+#include "llvm/InitializePasses.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
#include "llvm/Transforms/Utils/Local.h"
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
index 343e4550e1d93..4ebb0f746f464 100644
--- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
@@ -32,11 +32,15 @@
#include "llvm/ADT/PostOrderIterator.h"
#include "llvm/ADT/Sequence.h"
#include "llvm/Analysis/AliasAnalysis.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachinePostDominators.h"
+#include "llvm/IR/Dominators.h"
+#include "llvm/InitializePasses.h"
#include "llvm/Support/DebugCounter.h"
#include "llvm/TargetParser/TargetParser.h"
+
using namespace llvm;
#define DEBUG_TYPE "si-insert-waitcnts"
diff --git a/llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp b/llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
index 3f7b0eab6bb8c..73a2d0a56aebe 100644
--- a/llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SILateBranchLowering.cpp
@@ -17,6 +17,7 @@
#include "SIMachineFunctionInfo.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/InitializePasses.h"
using namespace llvm;
diff --git a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
index 09b737c4e9c16..1a91bbd433553 100644
--- a/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
@@ -24,6 +24,7 @@
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/InitializePasses.h"
using namespace llvm;
diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
index 0e2ac495d2d98..41402bd5278c6 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
@@ -80,6 +80,7 @@
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineLoopInfo.h"
#include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/IR/Dominators.h"
using namespace llvm;
diff --git a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
index 38d9a4b82daee..ecfaa5c70e9d3 100644
--- a/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
+++ b/llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/RegisterClassInfo.h"
#include "llvm/CodeGen/VirtRegMap.h"
+#include "llvm/InitializePasses.h"
using namespace llvm;
diff --git a/llvm/unittests/Target/AMDGPU/CSETest.cpp b/llvm/unittests/Target/AMDGPU/CSETest.cpp
index 3de5b88599649..ff44ff184234c 100644
--- a/llvm/unittests/Target/AMDGPU/CSETest.cpp
+++ b/llvm/unittests/Target/AMDGPU/CSETest.cpp
@@ -10,6 +10,7 @@
#include "AMDGPUUnitTests.h"
#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
#include "llvm/CodeGen/GlobalISel/CSEMIRBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
#include "gtest/gtest.h"
using namespace llvm;
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