[llvm] [AArch64] AArch64TargetLowering::computeKnownBitsForTargetNode - add support for AArch64ISD::MOV/MVN constants (PR #154039)

[Yatao Wang via llvm-commits]

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@@ -8,14 +8,14 @@ define <4 x i16> @fold_urem_vec_1(<4 x i16> %x) {
 ; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI0_0]
 ; CHECK-NEXT:    adrp x8, .LCPI0_1
 ; CHECK-NEXT:    ldr d2, [x8, :lo12:.LCPI0_1]
-; CHECK-NEXT:    adrp x8, .LCPI0_2
-; CHECK-NEXT:    ushl v1.4h, v0.4h, v1.4h
-; CHECK-NEXT:    umull v1.4s, v1.4h, v2.4h
-; CHECK-NEXT:    movi d2, #0000000000000000
-; CHECK-NEXT:    shrn v1.4h, v1.4s, #16
-; CHECK-NEXT:    fneg d2, d2
-; CHECK-NEXT:    sub v3.4h, v0.4h, v1.4h
-; CHECK-NEXT:    umull v2.4s, v3.4h, v2.4h
+; CHECK-NEXT:    mov     x8, #-9223372036854775808       // =0x8000000000000000
+; CHECK-NEXT:    ushl    v1.4h, v0.4h, v1.4h
+; CHECK-NEXT:    fmov    d3, x8
+; CHECK-NEXT:    adrp    x8, .LCPI0_2
+; CHECK-NEXT:    umull   v1.4s, v1.4h, v2.4h
+; CHECK-NEXT:    shrn    v1.4h, v1.4s, #16
+; CHECK-NEXT:    sub     v2.4h, v0.4h, v1.4h
+; CHECK-NEXT:    umull   v2.4s, v2.4h, v3.4h
----------------
ningxinr wrote:

> Can you add fneg(zero) as a canonical constant pattern.

Hi David,

Thanks for the feedback! Are you saying that for the following pattern:
```
movi d2, #0000000000000000
fneg d2, d2
```

`SelectionDAG::computeKnownBits` should be able to pick up the `fneg(zero)` pattern and decide that the KnownBit should look like `0x80` (for 8 bit int), or `0x8000` (for 16 bit int) etc... 

https://github.com/llvm/llvm-project/pull/154039