[llvm] [AArch64][llvm] Disassemble instructions in `SYS` alias encoding space correctly (PR #153905)

[Jonathan Thackray via llvm-commits]

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@@ -1017,13 +1018,24 @@ bool AArch64InstPrinter::printSysAlias(const MCInst *MI,
   else
     return false;
 
+  StringRef Reg = getRegisterName(MI->getOperand(4).getReg());
+  bool NotXZR = Reg != "xzr";
+
+  // If a mandatory or optional register is not specified in the TableGen
+  // (i.e. no register operand should be present), and the register value
+  // is not xzr/x31, then disassemble to a SYS alias instead.
+  if (NotXZR && !NeedsReg && !OptionalReg)
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jthackray wrote:

Actually, I've removed the optional register handling code, since it doesn't block multiple (pending) upstream code changes, and I'll re-add this later. This also makes it clearer exactly what this change is about (i.e. only one behaviour change)

https://github.com/llvm/llvm-project/pull/153905