[llvm] [RISCV] Generate QC_INSB/QC_INSBI instructions from OR of AND Imm (PR #154023)

[Sudharsan Veeravalli via llvm-commits]

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@@ -720,6 +720,74 @@ bool RISCVDAGToDAGISel::trySignedBitfieldInsertInMask(SDNode *Node) {
   return true;
 }
 
+// Generate a QC_INSB/QC_INSBI from 'or (and X, MaskImm), OrImm' iff the value
+// being inserted only sets known zero bits.
+bool RISCVDAGToDAGISel::tryBitfieldInsertOpFromOrAndImm(SDNode *Node) {
+  // Supported only in Xqcibm for now.
+  if (!Subtarget->hasVendorXqcibm())
+    return false;
+
+  auto *N1C = dyn_cast<ConstantSDNode>(Node->getOperand(1));
+  if (!N1C)
+    return false;
+
+  SDValue And = Node->getOperand(0);
+
+  if (And.getOpcode() != ISD::AND)
+    return false;
+
+  auto *N2C = dyn_cast<ConstantSDNode>(And->getOperand(1));
+  if (!And.hasOneUse() || !N2C)
+    return false;
+
+  int32_t OrImm = N1C->getSExtValue();
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svs-quic wrote:

I had taken the code directly from AArch64. Modified to use APInt now.

https://github.com/llvm/llvm-project/pull/154023