[llvm] [AMDGPU] Add support for store to constant address space (PR #153835)

[Matt Arsenault via llvm-commits]

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@@ -3910,10 +3910,14 @@ SDValue AMDGPUTargetLowering::performLoadCombine(SDNode *N,
 // type.
 SDValue AMDGPUTargetLowering::performStoreCombine(SDNode *N,
                                                   DAGCombinerInfo &DCI) const {
+  StoreSDNode *SN = cast<StoreSDNode>(N);
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arsenm wrote:

You can't do this in performStoreCombine, this needs to be universal custom lowering or direct selection. I think the easiest approach would be to just stop special casing the address space lists in the store patterns. 
e.g. we have 
`def StoreAddress_global : AddressSpaceList<[ AddrSpaces.Global ]>;`

and can just replace this with the load version 

https://github.com/llvm/llvm-project/pull/153835