[llvm] [SelectionDAGBuilder] Look for approriate INLINEASM_BR instruction to verify (PR #152591)

[via llvm-commits]

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@@ -12731,23 +12731,37 @@ void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) {
 // increase in virtreg number from there. If a callbr has no outputs, then it
 // should not have a corresponding callbr landingpad; in fact, the callbr
 // landingpad would not even be able to refer to such a callbr.
-static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg) {
+static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg,
+                                MachineBasicBlock *CallBrMBB) {
   MachineInstr *MI = MRI.def_begin(Reg)->getParent();
   // There is definitely at least one copy.
   assert(MI->getOpcode() == TargetOpcode::COPY &&
          "start of copy chain MUST be COPY");
   Reg = MI->getOperand(1).getReg();
+
+  // If the copied register in the first copy must be virtual.
+  assert(Reg.isVirtual() && "expected COPY of virtual register");
   MI = MRI.def_begin(Reg)->getParent();
+
   // There may be an optional second copy.
   if (MI->getOpcode() == TargetOpcode::COPY) {
     assert(Reg.isVirtual() && "expected COPY of virtual register");
     Reg = MI->getOperand(1).getReg();
     assert(Reg.isPhysical() && "expected COPY of physical register");
-    MI = MRI.def_begin(Reg)->getParent();
+
+    // Look for the machine callbr instruction.
+    for (auto Def : MRI.def_operands(Reg))
+      if (Def.getParent()->getOpcode() == TargetOpcode::INLINEASM_BR &&
+          Def.getParent()->getParent() == CallBrMBB) {
+        MI = Def.getParent();
+        break;
+      }
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XChy wrote:

Tracking the relationship between the output register and the callbr instruction still requires seeing the selected block of the callbr instruction. We may be able to scan the block in FunctionLoweringInfo, but it is not worthwhile to me. Maybe we can drop the verification for the second case in the comment. What's your opinion? @arsenm 

https://github.com/llvm/llvm-project/pull/152591