[llvm] [AMDGPU][MC] GFX9 - allow op_sel in v_interp_p2_f16 (PR #150712)

[Joe Nash via llvm-commits]

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@@ -566,6 +566,36 @@ v_interp_p2_f16 v5, v2, attr0.x, v3 clamp
 // NOSICI: :[[@LINE-2]]:{{[0-9]+}}: error: instruction not supported on this GPU
 // VI: v_interp_p2_f16 v5, v2, attr0.x, v3 clamp ; encoding: [0x05,0x80,0x76,0xd2,0x00,0x04,0x0e,0x04]
 
+v_interp_p2_f16 v5, v2, attr0.x, v3 op_sel:[1]
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Sisyph wrote:

I think the convention here is to pass whatever op_sel bits were input to the output, not drop them. For comparison, sp3 assembler takes whatever opsel bits you specified, and puts them in the output. We do the same for v_pack_b32_f16 on gfx9. On newer targets, especially in true16 mode, we tend to give an assembler error when opsel bit is not supported on a certain. But what this does, just dropping the bits that are non-functional, is not what we usually do. 

https://github.com/llvm/llvm-project/pull/150712