[clang] [llvm] [RISC-V]Implement -m{,no}fence-tso (PR #151638)

[Jessica Clarke via llvm-commits]

jrtc27 wrote:

https://github.com/gcc-mirror/gcc/commit/a6114c2a691112f9cf5b072c21685d2e43c76d81 for what it's worth.

I continue to believe that, for S/U-mode, the only correct thing to do is to upgrade your firmware. I could be persuaded that there's a need to support this hardware in M-mode where it may be difficult to support using C(++)11 atomics by emulating in a trap handler, e.g. if you need to perform an atomic update in some kind of critical section.

https://github.com/llvm/llvm-project/pull/151638