[llvm] PreISelIntrinsicLowering: Lower llvm.log to a loop if scalable vec arg (PR #129744)
Stephen Long via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 8 09:06:37 PDT 2025
https://github.com/steplong updated https://github.com/llvm/llvm-project/pull/129744
>From 79e1e13ae139f2e8e55623b17adaf7c946b14662 Mon Sep 17 00:00:00 2001
From: Stephen Long <steplong at quicinc.com>
Date: Tue, 4 Mar 2025 08:54:24 -0800
Subject: [PATCH 1/4] PreISelIntrinsicLowering: Lower llvm.log to a loop if
scalable vec arg
Similar to ab976a1, but for llvm.log.
---
llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp | 4 +-
llvm/lib/CodeGen/TargetLoweringBase.cpp | 2 +
.../AArch64/expand-log.ll | 43 +++++++++++++++++++
3 files changed, 48 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
diff --git a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
index 8de2c48581a1e..ed19bd95e44aa 100644
--- a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+++ b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
@@ -587,13 +587,15 @@ bool PreISelIntrinsicLowering::lowerIntrinsics(Module &M) const {
break;
case Intrinsic::exp:
case Intrinsic::exp2:
+ case Intrinsic::log:
Changed |= forEachCall(F, [&](CallInst *CI) {
Type *Ty = CI->getArgOperand(0)->getType();
if (!isa<ScalableVectorType>(Ty))
return false;
const TargetLowering *TL = TM->getSubtargetImpl(F)->getTargetLowering();
unsigned Op = TL->IntrinsicIDToISD(F.getIntrinsicID());
- if (!TL->isOperationExpand(Op, EVT::getEVT(Ty)))
+ if (Op == ISD::DELETED_NODE ||
+ !TL->isOperationExpand(Op, EVT::getEVT(Ty)))
return false;
return lowerUnaryVectorIntrinsicAsLoop(M, CI);
});
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index bf4c9f91d1c97..ced0d88c854c4 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -1923,6 +1923,8 @@ int TargetLoweringBase::IntrinsicIDToISD(Intrinsic::ID ID) const {
return ISD::FEXP;
case Intrinsic::exp2:
return ISD::FEXP2;
+ case Intrinsic::log:
+ return ISD::FLOG;
default:
return ISD::DELETED_NODE;
}
diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
new file mode 100644
index 0000000000000..424729f498aa6
--- /dev/null
+++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
@@ -0,0 +1,43 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
+; RUN: opt -passes=pre-isel-intrinsic-lowering -S < %s | FileCheck %s
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
+target triple = "aarch64"
+
+define <vscale x 4 x float> @scalable_vec_log(<vscale x 4 x float> %input) {
+; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_log(
+; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) {
+; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 4
+; CHECK-NEXT: br label %[[BB3:.*]]
+; CHECK: [[BB3]]:
+; CHECK-NEXT: [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
+; CHECK-NEXT: [[TMP5:%.*]] = phi <vscale x 4 x float> [ [[INPUT]], [[TMP0]] ], [ [[TMP8:%.*]], %[[BB3]] ]
+; CHECK-NEXT: [[TMP6:%.*]] = extractelement <vscale x 4 x float> [[TMP5]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP7:%.*]] = call float @llvm.log.f32(float [[TMP6]])
+; CHECK-NEXT: [[TMP8]] = insertelement <vscale x 4 x float> [[TMP5]], float [[TMP7]], i64 [[TMP4]]
+; CHECK-NEXT: [[TMP9]] = add i64 [[TMP4]], 1
+; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], [[TMP2]]
+; CHECK-NEXT: br i1 [[TMP10]], label %[[BB11:.*]], label %[[BB3]]
+; CHECK: [[BB11]]:
+; CHECK-NEXT: ret <vscale x 4 x float> [[TMP8]]
+;
+ %output = call <vscale x 4 x float> @llvm.log.nxv4f32(<vscale x 4 x float> %input)
+ ret <vscale x 4 x float> %output
+}
+
+define <4 x float> @fixed_vec_log(<4 x float> %input) {
+; CHECK-LABEL: define <4 x float> @fixed_vec_log(
+; CHECK-SAME: <4 x float> [[INPUT:%.*]]) {
+; CHECK-NEXT: [[OUTPUT:%.*]] = call <4 x float> @llvm.log.v4f32(<4 x float> [[INPUT]])
+; CHECK-NEXT: ret <4 x float> [[OUTPUT]]
+;
+ %output = call <4 x float> @llvm.log.v4f32(<4 x float> %input)
+ ret <4 x float> %output
+}
+
+declare <4 x float> @llvm.log.v4f32(<4 x float>) #0
+declare <vscale x 4 x float> @llvm.log.nxv4f32(<vscale x 4 x float>) #0
+
+; CHECK: attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+; CHECK-NEXT: attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
>From 0487ff9bfcf1f247fd0918a042ffa0a1ee456b34 Mon Sep 17 00:00:00 2001
From: Stephen Long <63318318+steplong at users.noreply.github.com>
Date: Fri, 8 Aug 2025 09:40:15 -0400
Subject: [PATCH 2/4] Update
llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
---
.../Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll | 1 -
1 file changed, 1 deletion(-)
diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
index 424729f498aa6..a91bd7e49ebde 100644
--- a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
+++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
@@ -1,6 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -passes=pre-isel-intrinsic-lowering -S < %s | FileCheck %s
-target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64"
define <vscale x 4 x float> @scalable_vec_log(<vscale x 4 x float> %input) {
>From 5b1b378134453dcb04f926412f2eef9cf73dfbe8 Mon Sep 17 00:00:00 2001
From: Stephen Long <steplong at quicinc.com>
Date: Fri, 8 Aug 2025 07:40:58 -0700
Subject: [PATCH 3/4] Add assert and remove unnecessary checks
---
llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp | 4 ++--
.../Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll | 2 --
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
index ed19bd95e44aa..9fa96e7372961 100644
--- a/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
+++ b/llvm/lib/CodeGen/PreISelIntrinsicLowering.cpp
@@ -594,8 +594,8 @@ bool PreISelIntrinsicLowering::lowerIntrinsics(Module &M) const {
return false;
const TargetLowering *TL = TM->getSubtargetImpl(F)->getTargetLowering();
unsigned Op = TL->IntrinsicIDToISD(F.getIntrinsicID());
- if (Op == ISD::DELETED_NODE ||
- !TL->isOperationExpand(Op, EVT::getEVT(Ty)))
+ assert(Op != ISD::DELETED_NODE && "unsupported intrinsic");
+ if (!TL->isOperationExpand(Op, EVT::getEVT(Ty)))
return false;
return lowerUnaryVectorIntrinsicAsLoop(M, CI);
});
diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
index a91bd7e49ebde..552c1fe8583a4 100644
--- a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
+++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
@@ -37,6 +37,4 @@ define <4 x float> @fixed_vec_log(<4 x float> %input) {
declare <4 x float> @llvm.log.v4f32(<4 x float>) #0
declare <vscale x 4 x float> @llvm.log.nxv4f32(<vscale x 4 x float>) #0
-; CHECK: attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
-; CHECK-NEXT: attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
>From 4900508f7730dc2e205364ad2d10ae370a497416 Mon Sep 17 00:00:00 2001
From: Stephen Long <steplong at quicinc.com>
Date: Fri, 8 Aug 2025 09:06:08 -0700
Subject: [PATCH 4/4] Fix failing test
---
.../Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
index 552c1fe8583a4..3a1d1324d8e45 100644
--- a/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
+++ b/llvm/test/Transforms/PreISelIntrinsicLowering/AArch64/expand-log.ll
@@ -6,7 +6,7 @@ define <vscale x 4 x float> @scalable_vec_log(<vscale x 4 x float> %input) {
; CHECK-LABEL: define <vscale x 4 x float> @scalable_vec_log(
; CHECK-SAME: <vscale x 4 x float> [[INPUT:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64()
-; CHECK-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 4
+; CHECK-NEXT: [[TMP2:%.*]] = mul nuw i64 [[TMP1]], 4
; CHECK-NEXT: br label %[[BB3:.*]]
; CHECK: [[BB3]]:
; CHECK-NEXT: [[TMP4:%.*]] = phi i64 [ 0, [[TMP0:%.*]] ], [ [[TMP9:%.*]], %[[BB3]] ]
More information about the llvm-commits
mailing list