[llvm] [AArch64] Support MI and PL (PR #150314)

[David Green via llvm-commits]

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@@ -11492,7 +11493,7 @@ SDValue AArch64TargetLowering::LowerSELECT_CC(
     ConstantSDNode *RHSVal = dyn_cast<ConstantSDNode>(RHS);
     if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&
         !RHSVal->isZero() && !RHSVal->isAllOnes()) {
-      AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
+      AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC, RHS);
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davemgreen wrote:

This can't be 0 because of the input condition?

https://github.com/llvm/llvm-project/pull/150314