[llvm] [M68k] Fix incorrect boolean content type (PR #152572)
Dan Salvato via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 7 14:52:04 PDT 2025
https://github.com/dansalvato updated https://github.com/llvm/llvm-project/pull/152572
>From 3565d7a6b17ee678c06583b26e636d61b774b385 Mon Sep 17 00:00:00 2001
From: Dan Salvato <dan at teamsalvato.com>
Date: Thu, 3 Jul 2025 00:11:11 -0600
Subject: [PATCH] [M68k] Fix incorrect boolean content type
M68k's SETCC instruction (`scc`) distinctly fills the destination byte
with all 1s. If boolean contents are set to `ZeroOrOneBooleanContent`,
LLVM can mistakenly think the destination holds `0x01` instead of `0xff`
and emit broken code as a result. This change corrects the boolean
content type to `ZeroOrNegativeOneBooleanContent`.
---
llvm/lib/Target/M68k/M68kISelLowering.cpp | 2 +-
llvm/test/CodeGen/M68k/Arith/add.ll | 6 ++--
.../CodeGen/M68k/Arith/smul-with-overflow.ll | 5 +--
llvm/test/CodeGen/M68k/Control/cmp.ll | 22 ++++++++----
.../CodeGen/M68k/Control/non-cmov-switch.ll | 34 ++++++++++++-------
llvm/test/CodeGen/M68k/Control/setcc.ll | 7 ++--
6 files changed, 50 insertions(+), 26 deletions(-)
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
index 594ea9f48c201..c6a20e211df7d 100644
--- a/llvm/lib/Target/M68k/M68kISelLowering.cpp
+++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -51,7 +51,7 @@ M68kTargetLowering::M68kTargetLowering(const M68kTargetMachine &TM,
MVT PtrVT = MVT::i32;
- setBooleanContents(ZeroOrOneBooleanContent);
+ setBooleanContents(ZeroOrNegativeOneBooleanContent);
auto *RegInfo = Subtarget.getRegisterInfo();
setStackPointerRegisterToSaveRestore(RegInfo->getStackRegister());
diff --git a/llvm/test/CodeGen/M68k/Arith/add.ll b/llvm/test/CodeGen/M68k/Arith/add.ll
index 417fe8f068479..73220c6eaf43e 100644
--- a/llvm/test/CodeGen/M68k/Arith/add.ll
+++ b/llvm/test/CodeGen/M68k/Arith/add.ll
@@ -85,9 +85,9 @@ define fastcc i32 @test9(i32 %x, i32 %y) nounwind readnone {
; CHECK: ; %bb.0:
; CHECK-NEXT: sub.l #10, %d0
; CHECK-NEXT: seq %d0
-; CHECK-NEXT: and.l #255, %d0
-; CHECK-NEXT: sub.l %d0, %d1
-; CHECK-NEXT: move.l %d1, %d0
+; CHECK-NEXT: ext.w %d0
+; CHECK-NEXT: ext.l %d0
+; CHECK-NEXT: add.l %d1, %d0
; CHECK-NEXT: rts
%cmp = icmp eq i32 %x, 10
%sub = sext i1 %cmp to i32
diff --git a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
index 423431750f20a..ad6843b310f06 100644
--- a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
@@ -102,8 +102,9 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind {
; CHECK-NEXT: suba.l #12, %sp
; CHECK-NEXT: muls.l %d1, %d0
; CHECK-NEXT: svs %d1
-; CHECK-NEXT: sub.b #1, %d1
-; CHECK-NEXT: bne .LBB4_2
+; CHECK-NEXT: and.b #1, %d1
+; CHECK-NEXT: cmpi.b #0, %d1
+; CHECK-NEXT: beq .LBB4_2
; CHECK-NEXT: ; %bb.1: ; %overflow
; CHECK-NEXT: lea (no,%pc), %a0
; CHECK-NEXT: move.l %a0, (%sp)
diff --git a/llvm/test/CodeGen/M68k/Control/cmp.ll b/llvm/test/CodeGen/M68k/Control/cmp.ll
index d3a8bbb0b0c8f..01dfaeb1b2ec2 100644
--- a/llvm/test/CodeGen/M68k/Control/cmp.ll
+++ b/llvm/test/CodeGen/M68k/Control/cmp.ll
@@ -84,6 +84,7 @@ define i64 @test3(i64 %x) nounwind {
; CHECK-NEXT: seq %d0
; CHECK-NEXT: move.l %d0, %d1
; CHECK-NEXT: and.l #255, %d1
+; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: moveq #0, %d0
; CHECK-NEXT: rts
%t = icmp eq i64 %x, 0
@@ -103,6 +104,7 @@ define i64 @test4(i64 %x) nounwind {
; CHECK-NEXT: subx.l %d0, %d1
; CHECK-NEXT: slt %d1
; CHECK-NEXT: and.l #255, %d1
+; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; CHECK-NEXT: adda.l #4, %sp
; CHECK-NEXT: rts
@@ -144,6 +146,7 @@ define i32 @test7(i64 %res) nounwind {
; CHECK-NEXT: cmpi.l #0, (4,%sp)
; CHECK-NEXT: seq %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: rts
entry:
%lnot = icmp ult i64 %res, 4294967296
@@ -158,6 +161,7 @@ define i32 @test8(i64 %res) nounwind {
; CHECK-NEXT: sub.l #3, %d0
; CHECK-NEXT: scs %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: rts
entry:
%lnot = icmp ult i64 %res, 12884901888
@@ -173,6 +177,7 @@ define i32 @test11(i64 %l) nounwind {
; CHECK-NEXT: sub.l #32768, %d0
; CHECK-NEXT: seq %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: rts
entry:
%shr.mask = and i64 %l, -140737488355328
@@ -240,6 +245,7 @@ define zeroext i1 @test15(i32 %bf.load, i32 %n) {
; CHECK-NEXT: or.b %d0, %d1
; CHECK-NEXT: move.l %d1, %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: rts
%bf.lshr = lshr i32 %bf.load, 16
%cmp2 = icmp eq i32 %bf.lshr, 0
@@ -288,20 +294,24 @@ define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) {
; CHECK-NEXT: ; %bb.0:
; CHECK-NEXT: suba.l #4, %sp
; CHECK-NEXT: .cfi_def_cfa_offset -8
-; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
+; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; CHECK-NEXT: move.l #16777215, %d0
; CHECK-NEXT: and.l (8,%sp), %d0
; CHECK-NEXT: sne %d1
; CHECK-NEXT: and.l #255, %d1
-; CHECK-NEXT: move.l (16,%sp), %a0
+; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: move.b (15,%sp), %d2
; CHECK-NEXT: and.l #255, %d2
; CHECK-NEXT: add.l %d1, %d2
-; CHECK-NEXT: sne (%a0)
+; CHECK-NEXT: sne %d1
+; CHECK-NEXT: and.b #1, %d1
+; CHECK-NEXT: move.l (16,%sp), %a0
+; CHECK-NEXT: move.b %d1, (%a0)
; CHECK-NEXT: cmpi.l #0, %d0
-; CHECK-NEXT: lea (d,%pc), %a0
-; CHECK-NEXT: sne (%a0)
-; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
+; CHECK-NEXT: sne %d0
+; CHECK-NEXT: and.b #1, %d0
+; CHECK-NEXT: move.b %d0, (d,%pc)
+; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; CHECK-NEXT: adda.l #4, %sp
; CHECK-NEXT: rts
%bf.shl = shl i32 %bf.load, 8
diff --git a/llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll b/llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
index 90d2be017ecdb..9c9033e02f48e 100644
--- a/llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
+++ b/llvm/test/CodeGen/M68k/Control/non-cmov-switch.ll
@@ -16,6 +16,7 @@ define internal void @select_i32(i32 %self, ptr nonnull %value) {
; CHECK-NEXT: bne .LBB0_2
; CHECK-NEXT: ; %bb.1: ; %start
; CHECK-NEXT: and.l #255, %d1
+; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: cmpi.l #0, %d1
; CHECK-NEXT: bne .LBB0_3
; CHECK-NEXT: .LBB0_2: ; %null
@@ -60,6 +61,7 @@ define internal void @select_i16(i16 %self, ptr nonnull %value) {
; CHECK-NEXT: bne .LBB1_2
; CHECK-NEXT: ; %bb.1: ; %start
; CHECK-NEXT: and.l #255, %d1
+; CHECK-NEXT: and.w #1, %d1
; CHECK-NEXT: cmpi.w #0, %d1
; CHECK-NEXT: bne .LBB1_3
; CHECK-NEXT: .LBB1_2: ; %null
@@ -93,18 +95,26 @@ define internal void @select_i8(i8 %self, ptr nonnull %value) {
; CHECK-LABEL: select_i8:
; CHECK: .cfi_startproc
; CHECK-NEXT: ; %bb.0: ; %start
-; CHECK-NEXT: move.l (8,%sp), %d0
-; CHECK-NEXT: cmpi.b #0, (7,%sp)
-; CHECK-NEXT: sne %d1
-; CHECK-NEXT: bne .LBB2_2
-; CHECK-NEXT: ; %bb.1: ; %start
-; CHECK-NEXT: cmpi.b #0, %d1
-; CHECK-NEXT: bne .LBB2_3
-; CHECK-NEXT: .LBB2_2: ; %null
-; CHECK-NEXT: suba.l %a0, %a0
-; CHECK-NEXT: move.l %d0, (%a0)
-; CHECK-NEXT: .LBB2_3: ; %exit
-; CHECK-NEXT: rts
+; CHECK-NEXT: suba.l #4, %sp
+; CHECK-NEXT: .cfi_def_cfa_offset -8
+; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
+; CHECK-NEXT: cmpi.b #0, (11,%sp)
+; CHECK-NEXT: move.w %ccr, %d2
+; CHECK-NEXT: sne %d1
+; CHECK-NEXT: move.l (12,%sp), %d0
+; CHECK-NEXT: move.w %d2, %ccr
+; CHECK-NEXT: bne .LBB2_2
+; CHECK-NEXT: ; %bb.1: ; %start
+; CHECK-NEXT: and.b #1, %d1
+; CHECK-NEXT: cmpi.b #0, %d1
+; CHECK-NEXT: bne .LBB2_3
+; CHECK-NEXT: .LBB2_2: ; %null
+; CHECK-NEXT: suba.l %a0, %a0
+; CHECK-NEXT: move.l %d0, (%a0)
+; CHECK-NEXT: .LBB2_3: ; %exit
+; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
+; CHECK-NEXT: adda.l #4, %sp
+; CHECK-NEXT: rts
start:
%2 = icmp eq i8 %self, 0
%3 = select i1 %2, i8 0, i8 1
diff --git a/llvm/test/CodeGen/M68k/Control/setcc.ll b/llvm/test/CodeGen/M68k/Control/setcc.ll
index 9e03f9b90842a..a2c24c94ca4cc 100644
--- a/llvm/test/CodeGen/M68k/Control/setcc.ll
+++ b/llvm/test/CodeGen/M68k/Control/setcc.ll
@@ -11,6 +11,7 @@ define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
; CHECK-NEXT: sub.l #26, %d0
; CHECK-NEXT: shi %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: lsl.l #5, %d0
; CHECK-NEXT: rts
entry:
@@ -27,6 +28,7 @@ define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
; CHECK-NEXT: sub.l #26, %d0
; CHECK-NEXT: scs %d0
; CHECK-NEXT: and.l #255, %d0
+; CHECK-NEXT: and.l #1, %d0
; CHECK-NEXT: lsl.l #5, %d0
; CHECK-NEXT: rts
entry:
@@ -39,16 +41,17 @@ define fastcc i64 @t3(i64 %x) nounwind readnone ssp {
; CHECK-LABEL: t3:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: suba.l #4, %sp
-; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
+; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill
; CHECK-NEXT: moveq #0, %d2
; CHECK-NEXT: sub.l #18, %d1
; CHECK-NEXT: subx.l %d2, %d0
; CHECK-NEXT: scs %d0
; CHECK-NEXT: move.l %d0, %d1
; CHECK-NEXT: and.l #255, %d1
+; CHECK-NEXT: and.l #1, %d1
; CHECK-NEXT: lsl.l #6, %d1
; CHECK-NEXT: move.l %d2, %d0
-; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
+; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload
; CHECK-NEXT: adda.l #4, %sp
; CHECK-NEXT: rts
entry:
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