[llvm] [AMDGPU] Recognise bitmask operations as srcmods on select (PR #152119)

[Stanislav Mekhanoshin via llvm-commits]

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@@ -3036,6 +3036,42 @@ bool AMDGPUDAGToDAGISel::SelectVOP3ModsImpl(SDValue In, SDValue &Src,
     Src = Src.getOperand(0);
   }
 
+  // Convert various sign-bit masks on integers to src mods. Currently disabled
+  // for 16-bit types as the codegen replaces the operand without adding a
+  // srcmod. This is intentionally finding the cases where we are performing
+  // float neg and abs on int types, the goal is not to obtain two's complement
+  // neg or abs. Limit converison to select operands via the nonCanonalizing
+  // pattern.
+  // TODO: Add 16-bit support.
+  if (IsCanonicalizing)
+    return true;
+
+  unsigned Opc = Src->getOpcode();
+  EVT VT = Src.getValueType();
+  if ((Opc != ISD::AND && Opc != ISD::OR && Opc != ISD::XOR) ||
+      (VT != MVT::i32 && VT != MVT::v2i32 && VT != MVT::i64))
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rampitec wrote:

I mean HW modifier flips one bit. Should this be used on an instruction with a real 64-bit operand only one bit would be flipped. In case of the v2i32 and a splat check this code would expect 2 bits to be affected: 32-th and 64-th. The problem here is that the matcher code does not know what is the intended instruction, a real 64-bit one or it will be split into two 32-bit instructions.

https://github.com/llvm/llvm-project/pull/152119