[llvm] [AArch64] Drop flags from BSP pseudos (PR #151856)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 7 09:35:19 PDT 2025
https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/151856
>From db1b3b4336dc67322701f2ba4aae9393a35f48c2 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Sun, 3 Aug 2025 09:01:13 +0100
Subject: [PATCH 1/2] [AArch64] Drop flags from BSP pseudos
This prevents cases where some of the operands match from hitting verifier
errorswith kill flags. These nodes should have been removed eariler in most
cases.
---
.../AArch64/AArch64ExpandPseudoInsts.cpp | 6 +++--
.../test/CodeGen/AArch64/bsp_implicit_ops.mir | 22 ++++++++++++++++++-
2 files changed, 25 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 201bfe0a443d6..77fcad634776d 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -1242,8 +1242,10 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
.addReg(DstReg,
RegState::Define |
getRenamableRegState(MI.getOperand(0).isRenamable()))
- .add(MI.getOperand(1))
- .add(MI.getOperand(1));
+ .addReg(MI.getOperand(1).getReg(),
+ getRenamableRegState(MI.getOperand(1).isRenamable()))
+ .addReg(MI.getOperand(1).getReg(),
+ getRenamableRegState(MI.getOperand(1).isRenamable()));
auto I2 =
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
diff --git a/llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir b/llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir
index 23ac67cac6416..7ba363d46a1ff 100644
--- a/llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir
+++ b/llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir
@@ -13,7 +13,7 @@ body: |
; CHECK-LABEL: name: BSL_COPY
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $q2 = ORRv16i8 killed renamable $q20, killed renamable $q20
+ ; CHECK-NEXT: renamable $q2 = ORRv16i8 renamable $q20, renamable $q20
; CHECK-NEXT: renamable $q2 = BSLv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
@@ -96,3 +96,23 @@ body: |
$q25 = ORRv16i8 $q3, killed $q3
RET_ReallyLR implicit $q22
...
+---
+name: DoubleOp
+tracksRegLiveness: true
+body: |
+ bb.0.entry:
+ liveins: $q2
+
+ ; CHECK-LABEL: name: DoubleOp
+ ; CHECK: liveins: $q2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: renamable $q0 = MOVIv8i16 1, 0
+ ; CHECK-NEXT: renamable $q1 = ORRv16i8 renamable $q2, renamable $q2
+ ; CHECK-NEXT: renamable $q1 = BSLv16i8 killed renamable $q1, renamable $q2, renamable $q0
+ ; CHECK-NEXT: renamable $q0 = SQADDv8i16 killed renamable $q1, killed renamable $q0
+ ; CHECK-NEXT: RET undef $lr, implicit $q0
+ renamable $q0 = MOVIv8i16 1, 0
+ renamable $q1 = BSPv16i8 killed renamable $q2, renamable $q2, renamable $q0
+ renamable $q0 = SQADDv8i16 killed renamable $q1, killed renamable $q0
+ RET_ReallyLR implicit $q0
+...
>From 4e0ec2168e954b3ff2fc3556f1e1415b5df6b9b8 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Thu, 7 Aug 2025 17:19:16 +0100
Subject: [PATCH 2/2] Attempt to be precise about the kill flags
---
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp | 12 ++++++++----
llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir | 2 +-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 77fcad634776d..d6a3d59b7ccfe 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -1236,16 +1236,20 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
.add(MI.getOperand(3));
transferImpOps(MI, I, I);
} else {
+ unsigned RegState =
+ getRenamableRegState(MI.getOperand(1).isRenamable()) |
+ getKillRegState(
+ MI.getOperand(1).isKill() &&
+ MI.getOperand(1).getReg() != MI.getOperand(2).getReg() &&
+ MI.getOperand(1).getReg() != MI.getOperand(3).getReg());
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::ORRv8i8
: AArch64::ORRv16i8))
.addReg(DstReg,
RegState::Define |
getRenamableRegState(MI.getOperand(0).isRenamable()))
- .addReg(MI.getOperand(1).getReg(),
- getRenamableRegState(MI.getOperand(1).isRenamable()))
- .addReg(MI.getOperand(1).getReg(),
- getRenamableRegState(MI.getOperand(1).isRenamable()));
+ .addReg(MI.getOperand(1).getReg(), RegState)
+ .addReg(MI.getOperand(1).getReg(), RegState);
auto I2 =
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == AArch64::BSPv8i8 ? AArch64::BSLv8i8
diff --git a/llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir b/llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir
index 7ba363d46a1ff..805d24475081e 100644
--- a/llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir
+++ b/llvm/test/CodeGen/AArch64/bsp_implicit_ops.mir
@@ -13,7 +13,7 @@ body: |
; CHECK-LABEL: name: BSL_COPY
; CHECK: liveins: $q20, $q21, $q22, $q23, $q6, $q1, $q7
; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: renamable $q2 = ORRv16i8 renamable $q20, renamable $q20
+ ; CHECK-NEXT: renamable $q2 = ORRv16i8 killed renamable $q20, killed renamable $q20
; CHECK-NEXT: renamable $q2 = BSLv16i8 killed renamable $q2, renamable $q21, renamable $q6, implicit killed $q21_q22_q23, implicit killed $q0_q1_q2_q3, implicit-def $q0_q1_q2_q3
; CHECK-NEXT: $q22 = ORRv16i8 $q0, killed $q0
; CHECK-NEXT: $q23 = ORRv16i8 $q1, killed $q1
More information about the llvm-commits
mailing list