[llvm] [WebAssembly] Optimize away mask of 63 for shl ( zext (and i32 63))) (PR #152397)

[Craig Topper via llvm-commits]

topperc wrote:

> i can move this to tablegen but i dont quite understand this point - `If the shift amount for an ISD::SHL is larger than 63 the result is considered poison.` If I don't change anything for any mask larger than 63, shouldn't it still be ok to be at DAGCombine?

If the shift amount is larger than 63, the mask will clear the upper bits to turn it into a value that is between 0 and 63. If you remove the mask without proving the upper bits are 0, then you might allow a value larger than 63 through to the shift.

https://github.com/llvm/llvm-project/pull/152397