[llvm] d1b6ce5 - [AMDGPU] gfx1250 has fixed GETPC bug and also extended VA to 57 bits (#152373)
via llvm-commits
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Wed Aug 6 13:32:29 PDT 2025
Author: Stanislav Mekhanoshin
Date: 2025-08-06T13:32:26-07:00
New Revision: d1b6ce50dffcc70cd1610515527b4645b1136d1c
URL: https://github.com/llvm/llvm-project/commit/d1b6ce50dffcc70cd1610515527b4645b1136d1c
DIFF: https://github.com/llvm/llvm-project/commit/d1b6ce50dffcc70cd1610515527b4645b1136d1c.diff
LOG: [AMDGPU] gfx1250 has fixed GETPC bug and also extended VA to 57 bits (#152373)
Added:
Modified:
llvm/lib/Target/AMDGPU/GCNSubtarget.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
index 1c3749d81eec8..c5bdd28314642 100644
--- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h
+++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h
@@ -1566,8 +1566,9 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
bool hasSetPrioIncWgInst() const { return HasSetPrioIncWgInst; }
// \returns true if S_GETPC_B64 zero-extends the result from 48 bits instead
- // of sign-extending.
- bool hasGetPCZeroExtension() const { return GFX12Insts; }
+ // of sign-extending. Note that GFX1250 has not only fixed the bug but also
+ // extended VA to 57 bits.
+ bool hasGetPCZeroExtension() const { return GFX12Insts && !GFX1250Insts; }
/// \returns SGPR allocation granularity supported by the subtarget.
unsigned getSGPRAllocGranule() const {
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