[llvm] [AArch64] Allow splitting bitmasks for EOR/ORR. (PR #150394)

[Ricardo Jesus via llvm-commits]

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@@ -190,19 +192,48 @@ static bool splitBitmaskImm(T Imm, unsigned RegSize, T &Imm1Enc, T &Imm2Enc) {
   return true;
 }
 
+template <typename T>
+static bool splitDisjointBitmaskImm(T Imm, unsigned RegSize, T &Imm1Enc,
+                                    T &Imm2Enc) {
+  assert(Imm && (Imm != ~static_cast<T>(0)) && "Invalid immediate!");
+
+  // Try to split a bitmask of the form 0b00000000011000000000011110000000 into
+  // two disjoint masks such as 0b00000000011000000000000000000000 and
+  // 0b00000000000000000000011110000000 where the inclusive/exclusive OR of the
+  // new masks match the original mask.
+  unsigned LowestBitSet = llvm::countr_zero(Imm);
+  unsigned LowestGapBitUnset =
+      LowestBitSet + llvm::countr_one(Imm >> LowestBitSet);
+
+  // Create a mask for the least significant group of consecutive ones.
+  assert(LowestGapBitUnset < sizeof(T) * CHAR_BIT && "Undefined behaviour!");
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rj-jesus wrote:

I added this assert to guard against UB, which could happen here if `Imm` was a run of 0s followed by a run of 1s. This is not a possible configuration currently as these cases should be caught by `trySplitLogicalImm`, but I thought it would be preferable to make this condition explicit. If anyone thinks otherwise, please let me know and I'll revert this; otherwise I'll merge this later.

https://github.com/llvm/llvm-project/pull/150394