[llvm] [Intrinsics][AArch64] Add intrinsic to mask off aliasing vector lanes (PR #117007)

[Sander de Smalen via llvm-commits]

================
@@ -374,6 +379,12 @@ SDValue DAGTypeLegalizer::PromoteIntRes_MERGE_VALUES(SDNode *N,
   return GetPromotedInteger(Op);
 }
 
+SDValue DAGTypeLegalizer::PromoteIntRes_LOOP_DEPENDENCE_MASK(SDNode *N) {
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sdesmalen-arm wrote:

I noticed that Widening and Splitting are not yet supported in this patch.

Widening just requires returning the same operation but then with a wider type.
Splitting requires doing some arithmetic with the pointers, e.g.
```
define <vscale x 8 x i1> @whilewr_nxv8i1_word(ptr %a, ptr %b) {
entry:
  %0 = call <vscale x 8 x i1> @llvm.loop.dependence.war.mask(ptr %a, ptr %b, i64 4)
  ret <vscale x 8 x i1> %0
}
```

would be equivalent to:
```
call <vscale x 4 x i1> @llvm.loop.dependence.war.mask(ptr %a, ptr %b, i64 4)
%a.hi = getelementptr inbounds <vscale x 4 x i32>, ptr %a, i64 1
call <vscale x 4 x i1> @llvm.loop.dependence.war.mask(ptr %a.hi, ptr %b, i64 4)
```

Can you add support for this in this PR?

https://github.com/llvm/llvm-project/pull/117007