[llvm] [GlobalISel] Support saturated truncate (PR #150219)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 6 02:49:56 PDT 2025
https://github.com/jyli0116 updated https://github.com/llvm/llvm-project/pull/150219
>From f7c40d6249cd3d8f98d21fdf540325519442c03c Mon Sep 17 00:00:00 2001
From: Yu Li <yu.li at arm.com>
Date: Wed, 23 Jul 2025 12:59:11 +0000
Subject: [PATCH 1/3] [GlobalISel] Support saturated truncate
---
.../llvm/CodeGen/GlobalISel/CombinerHelper.h | 19 +++
.../CodeGen/GlobalISel/GenericMachineInstrs.h | 27 ++++
.../llvm/CodeGen/GlobalISel/MIPatternMatch.h | 12 ++
.../include/llvm/Target/GlobalISel/Combine.td | 28 +++-
.../Target/GlobalISel/SelectionDAGCompat.td | 3 +
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 128 ++++++++++++++++++
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 3 +
.../GlobalISel/legalizer-info-validation.mir | 14 +-
llvm/test/CodeGen/AArch64/truncsat.ll | 79 +++++++++++
9 files changed, 306 insertions(+), 7 deletions(-)
create mode 100644 llvm/test/CodeGen/AArch64/truncsat.ll
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
index da829046cc421..590843a9c4dda 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
@@ -726,6 +726,25 @@ class CombinerHelper {
bool matchUMulHToLShr(MachineInstr &MI) const;
void applyUMulHToLShr(MachineInstr &MI) const;
+ // Combine trunc(smin(smax(x, C1), C2)) -> truncssat_s(x)
+ // or trunc(smax(smin(x, C2), C1)) -> truncssat_s(x).
+ bool matchTruncSSatS(MachineInstr &MI, Register &MatchInfo) const;
+ void applyTruncSSatS(MachineInstr &MI, Register &MatchInfo) const;
+
+ // Combine trunc(smin(smax(x, 0), C)) -> truncssat_u(x)
+ // or trunc(smax(smin(x, C), 0)) -> truncssat_u(x)
+ // or trunc(umin(smax(x, 0), C)) -> truncssat_u(x)
+ bool matchTruncSSatU(MachineInstr &MI, Register &MatchInfo) const;
+ void applyTruncSSatU(MachineInstr &MI, Register &MatchInfo) const;
+
+ // Combine trunc(umin(x, C)) -> truncusat_u(x).
+ bool matchTruncUSatU(MachineInstr &MI, Register &MatchInfo) const;
+ void applyTruncUSatU(MachineInstr &MI, Register &MatchInfo) const;
+
+ // Combine truncusat_u(fptoui(x)) -> fptoui_sat(x)
+ bool matchTruncUSatUToFPTOUISat(MachineInstr &MI, Register &MatchInfo) const;
+ void applyTruncUSatUToFPTOUISat(MachineInstr &MI, Register &MatchInfo) const;
+
/// Try to transform \p MI by using all of the above
/// combine functions. Returns true if changed.
bool tryCombine(MachineInstr &MI) const;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
index 4292c0b31c750..e9bbad16e5e6c 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
@@ -874,6 +874,9 @@ class GCastOp : public GenericMachineInstr {
case TargetOpcode::G_SEXT:
case TargetOpcode::G_SITOFP:
case TargetOpcode::G_TRUNC:
+ case TargetOpcode::G_TRUNC_SSAT_S:
+ case TargetOpcode::G_TRUNC_SSAT_U:
+ case TargetOpcode::G_TRUNC_USAT_U:
case TargetOpcode::G_UITOFP:
case TargetOpcode::G_ZEXT:
case TargetOpcode::G_ANYEXT:
@@ -916,6 +919,30 @@ class GTrunc : public GCastOp {
};
};
+/// Represents a saturated trunc from a signed input to a signed result.
+class GTruncSSatS : public GCastOp {
+public:
+ static bool classof(const MachineInstr *MI) {
+ return MI->getOpcode() == TargetOpcode::G_TRUNC_SSAT_S;
+ };
+};
+
+/// Represents a saturated trunc from a signed input to an unsigned result.
+class GTruncSSatU : public GCastOp {
+public:
+ static bool classof(const MachineInstr *MI) {
+ return MI->getOpcode() == TargetOpcode::G_TRUNC_SSAT_U;
+ };
+};
+
+/// Represents a saturated trunc from an unsigned input to an unsigned result.
+class GTruncUSatU : public GCastOp {
+public:
+ static bool classof(const MachineInstr *MI) {
+ return MI->getOpcode() == TargetOpcode::G_TRUNC_USAT_U;
+ };
+};
+
/// Represents a vscale.
class GVScale : public GenericMachineInstr {
public:
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
index 827cdbdb23c51..829e4eeed7519 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
@@ -740,6 +740,18 @@ m_GFPTrunc(const SrcTy &Src) {
return UnaryOp_match<SrcTy, TargetOpcode::G_FPTRUNC>(Src);
}
+template <typename SrcTy>
+inline UnaryOp_match<SrcTy, TargetOpcode::G_FPTOSI>
+m_GFPToSI(const SrcTy &Src) {
+ return UnaryOp_match<SrcTy, TargetOpcode::G_FPTOSI>(Src);
+}
+
+template <typename SrcTy>
+inline UnaryOp_match<SrcTy, TargetOpcode::G_FPTOUI>
+m_GFPToUI(const SrcTy &Src) {
+ return UnaryOp_match<SrcTy, TargetOpcode::G_FPTOUI>(Src);
+}
+
template <typename SrcTy>
inline UnaryOp_match<SrcTy, TargetOpcode::G_FABS> m_GFabs(const SrcTy &Src) {
return UnaryOp_match<SrcTy, TargetOpcode::G_FABS>(Src);
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
index b619de39a8c75..fba5c480ca461 100644
--- a/llvm/include/llvm/Target/GlobalISel/Combine.td
+++ b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1243,6 +1243,32 @@ def mulh_to_lshr : GICombineRule<
def mulh_combines : GICombineGroup<[mulh_to_lshr]>;
+def trunc_ssats : GICombineRule<
+ (defs root:$root, register_matchinfo:$matchinfo),
+ (match (G_TRUNC $dst, $src):$root,
+ [{ return Helper.matchTruncSSatS(*${root}, ${matchinfo}); }]),
+ (apply [{ Helper.applyTruncSSatS(*${root}, ${matchinfo}); }])>;
+
+def trunc_ssatu : GICombineRule<
+ (defs root:$root, register_matchinfo:$matchinfo),
+ (match (G_TRUNC $dst, $src):$root,
+ [{ return Helper.matchTruncSSatU(*${root}, ${matchinfo}); }]),
+ (apply [{ Helper.applyTruncSSatU(*${root}, ${matchinfo}); }])>;
+
+def trunc_usatu : GICombineRule<
+ (defs root:$root, register_matchinfo:$matchinfo),
+ (match (G_TRUNC $dst, $src):$root,
+ [{ return Helper.matchTruncUSatU(*${root}, ${matchinfo}); }]),
+ (apply [{ Helper.applyTruncUSatU(*${root}, ${matchinfo}); }])>;
+
+def truncusatu_to_fptouisat : GICombineRule<
+ (defs root:$root, register_matchinfo:$matchinfo),
+ (match (G_TRUNC_USAT_U $dst, $src):$root,
+ [{ return Helper.matchTruncUSatUToFPTOUISat(*${root}, ${matchinfo}); }]),
+ (apply [{ Helper.applyTruncUSatUToFPTOUISat(*${root}, ${matchinfo}); }])>;
+
+def truncsat_combines : GICombineGroup<[trunc_ssats, trunc_ssatu, trunc_usatu, truncusatu_to_fptouisat]>;
+
def redundant_neg_operands: GICombineRule<
(defs root:$root, build_fn_matchinfo:$matchinfo),
(match (wip_match_opcode G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMAD, G_FMA):$root,
@@ -2067,7 +2093,7 @@ def all_combines : GICombineGroup<[integer_reassoc_combines, trivial_combines,
fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors,
simplify_neg_minmax, combine_concat_vector,
sext_trunc, zext_trunc, prefer_sign_combines, shuffle_combines,
- combine_use_vector_truncate, merge_combines, overflow_combines]>;
+ combine_use_vector_truncate, merge_combines, overflow_combines, truncsat_combines]>;
// A combine group used to for prelegalizer combiners at -O0. The combines in
// this group have been selected based on experiments to balance code size and
diff --git a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
index b65a63b5108dc..c0d480294dd8b 100644
--- a/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
+++ b/llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
@@ -51,6 +51,9 @@ def : GINodeEquiv<G_SEXT, sext>;
def : GINodeEquiv<G_SEXT_INREG, sext_inreg>;
def : GINodeEquiv<G_ZEXT, zext>;
def : GINodeEquiv<G_TRUNC, trunc>;
+def : GINodeEquiv<G_TRUNC_SSAT_S, truncssat_s>;
+def : GINodeEquiv<G_TRUNC_SSAT_U, truncssat_u>;
+def : GINodeEquiv<G_TRUNC_USAT_U, truncusat_u>;
def : GINodeEquiv<G_BITCAST, bitconvert>;
// G_INTTOPTR - SelectionDAG has no equivalent.
// G_PTRTOINT - SelectionDAG has no equivalent.
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index e84ba91c47c8b..0d2debf08227e 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -5844,6 +5844,134 @@ void CombinerHelper::applyUMulHToLShr(MachineInstr &MI) const {
MI.eraseFromParent();
}
+bool CombinerHelper::matchTruncSSatS(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+ unsigned NumDstBits = DstTy.getScalarSizeInBits();
+ unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
+ assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
+
+ APInt MinConst, MaxConst;
+ APInt SignedMax = APInt::getSignedMaxValue(NumDstBits).sext(NumSrcBits);
+ APInt SignedMin = APInt::getSignedMinValue(NumDstBits).sext(NumSrcBits);
+
+ if (isLegal({TargetOpcode::G_TRUNC_SSAT_S, {DstTy, SrcTy}})) {
+ if (mi_match(Src, MRI,
+ m_GSMin(m_GSMax(m_Reg(MatchInfo), m_ICstOrSplat(MinConst)),
+ m_ICstOrSplat(MaxConst))) &&
+ APInt::isSameValue(MinConst, SignedMin) &&
+ APInt::isSameValue(MaxConst, SignedMax))
+ return true;
+ if (mi_match(Src, MRI,
+ m_GSMax(m_GSMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst)),
+ m_ICstOrSplat(MinConst))) &&
+ APInt::isSameValue(MinConst, SignedMin) &&
+ APInt::isSameValue(MaxConst, SignedMax))
+ return true;
+ }
+ return false;
+}
+
+void CombinerHelper::applyTruncSSatS(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Builder.buildTruncSSatS(Dst, MatchInfo);
+ MI.eraseFromParent();
+}
+
+bool CombinerHelper::matchTruncSSatU(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+ unsigned NumDstBits = DstTy.getScalarSizeInBits();
+ unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
+ assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
+
+ APInt MaxConst;
+ APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
+
+ if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
+ if (mi_match(Src, MRI,
+ m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
+ m_ICstOrSplat(MaxConst))) &&
+ APInt::isSameValue(MaxConst, UnsignedMax))
+ return true;
+ if (mi_match(Src, MRI,
+ m_GSMax(m_GSMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst)),
+ m_SpecificICstOrSplat(0))) &&
+ APInt::isSameValue(MaxConst, UnsignedMax))
+ return true;
+ if (mi_match(Src, MRI,
+ m_GUMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
+ m_ICstOrSplat(MaxConst))) &&
+ APInt::isSameValue(MaxConst, UnsignedMax))
+ return true;
+ }
+ return false;
+}
+
+void CombinerHelper::applyTruncSSatU(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Builder.buildTruncSSatU(Dst, MatchInfo);
+ MI.eraseFromParent();
+}
+
+bool CombinerHelper::matchTruncUSatU(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+ unsigned NumDstBits = DstTy.getScalarSizeInBits();
+ unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
+ assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
+
+ APInt MaxConst;
+ APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
+
+ if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
+ if (mi_match(Src, MRI,
+ m_GUMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst))) &&
+ APInt::isSameValue(MaxConst, UnsignedMax))
+ return true;
+ }
+ return false;
+}
+
+void CombinerHelper::applyTruncUSatU(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Builder.buildTruncUSatU(Dst, MatchInfo);
+ MI.eraseFromParent();
+}
+
+bool CombinerHelper::matchTruncUSatUToFPTOUISat(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Register Src = MI.getOperand(1).getReg();
+ LLT DstTy = MRI.getType(Dst);
+ LLT SrcTy = MRI.getType(Src);
+
+ if (isLegalOrBeforeLegalizer({TargetOpcode::G_FPTOUI_SAT, {DstTy, SrcTy}})) {
+ if (mi_match(Src, MRI, m_GFPToUI((m_Reg(MatchInfo)))))
+ return true;
+ }
+ return false;
+}
+
+void CombinerHelper::applyTruncUSatUToFPTOUISat(MachineInstr &MI,
+ Register &MatchInfo) const {
+ Register Dst = MI.getOperand(0).getReg();
+ Builder.buildFPTOUI_SAT(Dst, MatchInfo);
+ MI.eraseFromParent();
+}
+
bool CombinerHelper::matchRedundantNegOperands(MachineInstr &MI,
BuildFnTy &MatchInfo) const {
unsigned Opc = MI.getOpcode();
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index e0e1af78770de..03840e33ac237 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -797,6 +797,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampMinNumElements(0, s16, 4)
.alwaysLegal();
+ getActionDefinitionsBuilder({G_TRUNC_SSAT_S, G_TRUNC_SSAT_U, G_TRUNC_USAT_U})
+ .legalFor({{v8s8, v8s16}, {v4s16, v4s32}, {v2s32, v2s64}});
+
getActionDefinitionsBuilder(G_SEXT_INREG)
.legalFor({s32, s64})
.legalFor(PackedVectorAllTypeList)
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 5c164bf672082..716665ee12c8d 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -321,14 +321,16 @@
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
# DEBUG-NEXT: G_TRUNC_SSAT_S (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. the first uncovered type index: 2, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_TRUNC_SSAT_U (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. the first uncovered type index: 2, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_TRUNC_USAT_U (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
-# DEBUG-NEXT: .. type index coverage check SKIPPED: no rules defined
-# DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
+# DEBUG-NEXT: .. the first uncovered type index: 2, OK
+# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
# DEBUG-NEXT: G_CONSTANT (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 1, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
diff --git a/llvm/test/CodeGen/AArch64/truncsat.ll b/llvm/test/CodeGen/AArch64/truncsat.ll
new file mode 100644
index 0000000000000..19779aba2697e
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/truncsat.ll
@@ -0,0 +1,79 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
+
+
+define <4 x i16> @ssats_1(<4 x i32> %x) {
+; CHECK-LABEL: ssats_1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
+ %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
+ %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
+ ret <4 x i16> %conv6
+}
+
+define <4 x i16> @ssats_2(<4 x i32> %x) {
+; CHECK-LABEL: ssats_2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
+ %spec.store.select7 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
+ %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
+ ret <4 x i16> %conv6
+}
+
+define <4 x i16> @ssatu_1(<4 x i32> %x) {
+; CHECK-LABEL: ssatu_1:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
+ %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)
+ %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
+ ret <4 x i16> %conv6
+}
+
+define <4 x i16> @ssatu_2(<4 x i32> %x) {
+; CHECK-LABEL: ssatu_2:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> zeroinitializer)
+ %spec.store.select7 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
+ %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
+ ret <4 x i16> %conv6
+}
+
+define <4 x i16> @ssatu_3(<4 x i32> %x) {
+; CHECK-LABEL: ssatu_3:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: sqxtun v0.4h, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> zeroinitializer)
+ %spec.store.select7 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
+ %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
+ ret <4 x i16> %conv6
+}
+
+define <4 x i16> @usatu(<4 x i32> %x) {
+; CHECK-LABEL: usatu:
+; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
+entry:
+ %spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %x, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
+ %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>
+ ret <4 x i16> %conv6
+}
+
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-GI: {{.*}}
+; CHECK-SD: {{.*}}
>From 4cc82c865730c60f89cbfa302c517009052f3361 Mon Sep 17 00:00:00 2001
From: Yu Li <yu.li at arm.com>
Date: Wed, 6 Aug 2025 09:42:06 +0000
Subject: [PATCH 2/3] resolved comments
---
.../lib/CodeGen/GlobalISel/CombinerHelper.cpp | 32 +-
llvm/lib/Target/AArch64/AArch64Combine.td | 2 +-
.../AArch64/GISel/AArch64LegalizerInfo.cpp | 9 +
llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll | 2678 +++++++++++++----
.../test/CodeGen/AArch64/fptosi-sat-vector.ll | 127 +-
.../test/CodeGen/AArch64/fptoui-sat-vector.ll | 102 +-
llvm/test/CodeGen/AArch64/qmovn.ll | 201 +-
llvm/test/CodeGen/AArch64/truncsat.ll | 79 -
8 files changed, 2297 insertions(+), 933 deletions(-)
delete mode 100644 llvm/test/CodeGen/AArch64/truncsat.ll
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 0d2debf08227e..11f7872f566a5 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -5854,22 +5854,16 @@ bool CombinerHelper::matchTruncSSatS(MachineInstr &MI,
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
- APInt MinConst, MaxConst;
APInt SignedMax = APInt::getSignedMaxValue(NumDstBits).sext(NumSrcBits);
APInt SignedMin = APInt::getSignedMinValue(NumDstBits).sext(NumSrcBits);
-
if (isLegal({TargetOpcode::G_TRUNC_SSAT_S, {DstTy, SrcTy}})) {
if (mi_match(Src, MRI,
- m_GSMin(m_GSMax(m_Reg(MatchInfo), m_ICstOrSplat(MinConst)),
- m_ICstOrSplat(MaxConst))) &&
- APInt::isSameValue(MinConst, SignedMin) &&
- APInt::isSameValue(MaxConst, SignedMax))
+ m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(SignedMin)),
+ m_SpecificICstOrSplat(SignedMax))))
return true;
if (mi_match(Src, MRI,
- m_GSMax(m_GSMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst)),
- m_ICstOrSplat(MinConst))) &&
- APInt::isSameValue(MinConst, SignedMin) &&
- APInt::isSameValue(MaxConst, SignedMax))
+ m_GSMax(m_GSMin(m_Reg(MatchInfo), m_SpecificICstOrSplat(SignedMax)),
+ m_SpecificICstOrSplat(SignedMin))))
return true;
}
return false;
@@ -5892,24 +5886,19 @@ bool CombinerHelper::matchTruncSSatU(MachineInstr &MI,
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
- APInt MaxConst;
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
-
if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
if (mi_match(Src, MRI,
m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
- m_ICstOrSplat(MaxConst))) &&
- APInt::isSameValue(MaxConst, UnsignedMax))
+ m_SpecificICstOrSplat(UnsignedMax))))
return true;
if (mi_match(Src, MRI,
- m_GSMax(m_GSMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst)),
- m_SpecificICstOrSplat(0))) &&
- APInt::isSameValue(MaxConst, UnsignedMax))
+ m_GSMax(m_GSMin(m_Reg(MatchInfo), m_SpecificICstOrSplat(UnsignedMax)),
+ m_SpecificICstOrSplat(0))))
return true;
if (mi_match(Src, MRI,
m_GUMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(0)),
- m_ICstOrSplat(MaxConst))) &&
- APInt::isSameValue(MaxConst, UnsignedMax))
+ m_SpecificICstOrSplat(UnsignedMax))))
return true;
}
return false;
@@ -5932,13 +5921,10 @@ bool CombinerHelper::matchTruncUSatU(MachineInstr &MI,
unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
assert(NumSrcBits > NumDstBits && "Unexpected types for truncate operation");
- APInt MaxConst;
APInt UnsignedMax = APInt::getMaxValue(NumDstBits).zext(NumSrcBits);
-
if (isLegal({TargetOpcode::G_TRUNC_SSAT_U, {DstTy, SrcTy}})) {
if (mi_match(Src, MRI,
- m_GUMin(m_Reg(MatchInfo), m_ICstOrSplat(MaxConst))) &&
- APInt::isSameValue(MaxConst, UnsignedMax))
+ m_GUMin(m_Reg(MatchInfo), m_SpecificICstOrSplat(UnsignedMax))))
return true;
}
return false;
diff --git a/llvm/lib/Target/AArch64/AArch64Combine.td b/llvm/lib/Target/AArch64/AArch64Combine.td
index 99f0af5f6a3f8..6820fc838ecf5 100644
--- a/llvm/lib/Target/AArch64/AArch64Combine.td
+++ b/llvm/lib/Target/AArch64/AArch64Combine.td
@@ -367,5 +367,5 @@ def AArch64PostLegalizerCombiner
select_to_minmax, or_to_bsp, combine_concat_vector,
commute_constant_to_rhs, extract_vec_elt_combines,
push_freeze_to_prevent_poison_from_propagating,
- combine_mul_cmlt, combine_use_vector_truncate, extmultomull]> {
+ combine_mul_cmlt, combine_use_vector_truncate, extmultomull, truncsat_combines]> {
}
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 03840e33ac237..eeb890b1cebc5 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -1841,6 +1841,15 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
return LowerTriOp(AArch64::G_UDOT);
case Intrinsic::aarch64_neon_sdot:
return LowerTriOp(AArch64::G_SDOT);
+ case Intrinsic::aarch64_neon_sqxtn: {
+ return LowerBinOp(TargetOpcode::G_TRUNC_SSAT_S);
+ }
+ case Intrinsic::aarch64_neon_sqxtun: {
+ return LowerBinOp(TargetOpcode::G_TRUNC_SSAT_U);
+ }
+ case Intrinsic::aarch64_neon_uqxtn: {
+ return LowerBinOp(TargetOpcode::G_TRUNC_USAT_U);
+ }
case Intrinsic::vector_reverse:
// TODO: Add support for vector_reverse
diff --git a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
index 9157bcba59e9b..b770ebb3c3fea 100644
--- a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-CVT
-; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FP16
+; RUN: llc < %s -mtriple=aarch64 -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-CVT-SD
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD,CHECK-FP16-SD
+; RUN: llc < %s -mtriple=aarch64 -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-CVT-GI
+; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI,CHECK-FP16-GI
; i32 saturate
@@ -21,15 +23,24 @@ entry:
}
define <2 x i32> @utest_f64i32(<2 x double> %x) {
-; CHECK-LABEL: utest_f64i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov d1, v0.d[1]
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fcvtzu w9, d1
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.s[1], w9
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utest_f64i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov d1, v0.d[1]
+; CHECK-SD-NEXT: fcvtzu w8, d0
+; CHECK-SD-NEXT: fcvtzu w9, d1
+; CHECK-SD-NEXT: fmov s0, w8
+; CHECK-SD-NEXT: mov v0.s[1], w9
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utest_f64i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
entry:
%conv = fptoui <2 x double> %x to <2 x i64>
%0 = icmp ult <2 x i64> %conv, <i64 4294967295, i64 4294967295>
@@ -55,10 +66,31 @@ entry:
}
define <4 x i32> @stest_f32i32(<4 x float> %x) {
-; CHECK-LABEL: stest_f32i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stest_f32i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stest_f32i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-GI-NEXT: adrp x8, .LCPI3_1
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI3_0
+; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI3_0]
+; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
@@ -70,10 +102,24 @@ entry:
}
define <4 x i32> @utest_f32i32(<4 x float> %x) {
-; CHECK-LABEL: utest_f32i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utest_f32i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utest_f32i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptoui <4 x float> %x to <4 x i64>
%0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -83,10 +129,28 @@ entry:
}
define <4 x i32> @ustest_f32i32(<4 x float> %x) {
-; CHECK-LABEL: ustest_f32i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ustest_f32i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ustest_f32i32:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -98,11 +162,62 @@ entry:
}
define <4 x i32> @stest_f16i32(<4 x half> %x) {
-; CHECK-LABEL: stest_f16i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stest_f16i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI6_1
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_1]
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI6_0
+; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f16i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI6_1
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_1]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI6_0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI6_0]
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>
@@ -114,11 +229,48 @@ entry:
}
define <4 x i32> @utesth_f16i32(<4 x half> %x) {
-; CHECK-LABEL: utesth_f16i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utesth_f16i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x half> %x to <4 x i64>
%0 = icmp ult <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -128,11 +280,56 @@ entry:
}
define <4 x i32> @ustest_f16i32(<4 x half> %x) {
-; CHECK-LABEL: ustest_f16i32:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ustest_f16i32:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i32:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i32:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, #0
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-FP16-GI-NEXT: and v1.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
%0 = icmp slt <4 x i64> %conv, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
@@ -146,15 +343,25 @@ entry:
; i16 saturate
define <2 x i16> @stest_f64i16(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: movi v1.2s, #127, msl #8
-; CHECK-NEXT: xtn v0.2s, v0.2d
-; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: mvni v1.2s, #127, msl #8
-; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stest_f64i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: movi v1.2s, #127, msl #8
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stest_f64i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: movi v1.2s, #127, msl #8
+; CHECK-GI-NEXT: mvni v2.2s, #127, msl #8
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: smax v0.2s, v0.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i32>
%0 = icmp slt <2 x i32> %conv, <i32 32767, i32 32767>
@@ -248,20 +455,30 @@ entry:
}
define <8 x i16> @stest_f16i16(<8 x half> %x) {
-; CHECK-CVT-LABEL: stest_f16i16:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-NEXT: sqxtn v0.4h, v1.4s
-; CHECK-CVT-NEXT: sqxtn2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f16i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: sqxtn2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-FP16-LABEL: stest_f16i16:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-GI-LABEL: stest_f16i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-GI-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-GI-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-GI-NEXT: sqxtn2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
%0 = icmp slt <8 x i32> %conv, <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>
@@ -273,20 +490,30 @@ entry:
}
define <8 x i16> @utesth_f16i16(<8 x half> %x) {
-; CHECK-CVT-LABEL: utesth_f16i16:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzu v2.4s, v0.4s
-; CHECK-CVT-NEXT: uqxtn v0.4h, v1.4s
-; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
+; CHECK-CVT-SD-LABEL: utesth_f16i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: uqxtn2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utesth_f16i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-FP16-LABEL: utesth_f16i16:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-GI-LABEL: utesth_f16i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-GI-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-GI-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-GI-NEXT: uqxtn2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptoui <8 x half> %x to <8 x i32>
%0 = icmp ult <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
@@ -296,20 +523,30 @@ entry:
}
define <8 x i16> @ustest_f16i16(<8 x half> %x) {
-; CHECK-CVT-LABEL: ustest_f16i16:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-NEXT: sqxtun v0.4h, v1.4s
-; CHECK-CVT-NEXT: sqxtun2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f16i16:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: sqxtun2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
;
-; CHECK-FP16-LABEL: ustest_f16i16:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-FP16-SD-LABEL: ustest_f16i16:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ustest_f16i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-GI-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-GI-NEXT: sqxtun v0.4h, v1.4s
+; CHECK-GI-NEXT: sqxtun2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
%0 = icmp slt <8 x i32> %conv, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
@@ -323,10 +560,72 @@ entry:
; i64 saturate
define <2 x i64> @stest_f64i64(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stest_f64i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stest_f64i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w21, -24
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w30, -40
+; CHECK-GI-NEXT: .cfi_offset b8, -48
+; CHECK-GI-NEXT: mov d8, v0.d[1]
+; CHECK-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: bl __fixdfti
+; CHECK-GI-NEXT: fmov d0, d8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixdfti
+; CHECK-GI-NEXT: cmp x19, x21
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lo
+; CHECK-GI-NEXT: cmp x20, #0
+; CHECK-GI-NEXT: cset w9, lt
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-GI-NEXT: cmp x0, x21
+; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: cmp x1, #0
+; CHECK-GI-NEXT: cset w10, lt
+; CHECK-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-GI-NEXT: cmp x8, x22
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: cset w13, ge
+; CHECK-GI-NEXT: cmn x10, #1
+; CHECK-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-GI-NEXT: cmp x9, x22
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: cset w13, ge
+; CHECK-GI-NEXT: cmn x11, #1
+; CHECK-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-GI-NEXT: tst w11, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
@@ -338,34 +637,68 @@ entry:
}
define <2 x i64> @utest_f64i64(<2 x double> %x) {
-; CHECK-LABEL: utest_f64i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov d0, v0.d[1]
-; CHECK-NEXT: bl __fixunsdfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: bl __fixunsdfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utest_f64i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: mov d0, v0.d[1]
+; CHECK-SD-NEXT: bl __fixunsdfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: bl __fixunsdfti
+; CHECK-SD-NEXT: cmp x1, #0
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-SD-NEXT: cmp x20, #0
+; CHECK-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utest_f64i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: mov d8, v0.d[1]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: bl __fixunsdfti
+; CHECK-GI-NEXT: fmov d0, d8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixunsdfti
+; CHECK-GI-NEXT: cmp x20, #1
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lo
+; CHECK-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-GI-NEXT: cmp x1, #1
+; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptoui <2 x double> %x to <2 x i128>
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -375,42 +708,92 @@ entry:
}
define <2 x i64> @ustest_f64i64(<2 x double> %x) {
-; CHECK-LABEL: ustest_f64i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov d0, v0.d[1]
-; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, lt
-; CHECK-NEXT: csinc x9, x1, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csel x10, x19, xzr, lt
-; CHECK-NEXT: csinc x11, x20, xzr, lt
-; CHECK-NEXT: cmp xzr, x10
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ngcs xzr, x11
-; CHECK-NEXT: csel x10, x10, xzr, lt
-; CHECK-NEXT: cmp xzr, x8
-; CHECK-NEXT: ngcs xzr, x9
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: csel x8, x8, xzr, lt
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ustest_f64i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: bl __fixdfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: mov d0, v0.d[1]
+; CHECK-SD-NEXT: bl __fixdfti
+; CHECK-SD-NEXT: cmp x1, #1
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-SD-NEXT: cmp x20, #1
+; CHECK-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-SD-NEXT: csinc x11, x20, xzr, lt
+; CHECK-SD-NEXT: cmp xzr, x10
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ngcs xzr, x11
+; CHECK-SD-NEXT: csel x10, x10, xzr, lt
+; CHECK-SD-NEXT: cmp xzr, x8
+; CHECK-SD-NEXT: ngcs xzr, x9
+; CHECK-SD-NEXT: fmov d0, x10
+; CHECK-SD-NEXT: csel x8, x8, xzr, lt
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ustest_f64i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: mov d8, v0.d[1]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: bl __fixdfti
+; CHECK-GI-NEXT: fmov d0, d8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixdfti
+; CHECK-GI-NEXT: cmp x20, #1
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lt
+; CHECK-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-GI-NEXT: cmp x1, #1
+; CHECK-GI-NEXT: cset w9, lt
+; CHECK-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-GI-NEXT: cmp x8, #0
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: cset w10, gt
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-GI-NEXT: cmp x9, #0
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: cset w11, gt
+; CHECK-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-GI-NEXT: tst w11, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -422,11 +805,74 @@ entry:
}
define <2 x i64> @stest_f32i64(<2 x float> %x) {
-; CHECK-LABEL: stest_f32i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stest_f32i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stest_f32i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w21, -24
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w30, -40
+; CHECK-GI-NEXT: .cfi_offset b8, -48
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov s8, v0.s[1]
+; CHECK-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-GI-NEXT: bl __fixsfti
+; CHECK-GI-NEXT: fmov s0, s8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixsfti
+; CHECK-GI-NEXT: cmp x19, x21
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lo
+; CHECK-GI-NEXT: cmp x20, #0
+; CHECK-GI-NEXT: cset w9, lt
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-GI-NEXT: cmp x0, x21
+; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: cmp x1, #0
+; CHECK-GI-NEXT: cset w10, lt
+; CHECK-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-GI-NEXT: cmp x8, x22
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: cset w13, ge
+; CHECK-GI-NEXT: cmn x10, #1
+; CHECK-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-GI-NEXT: cmp x9, x22
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: cset w13, ge
+; CHECK-GI-NEXT: cmn x11, #1
+; CHECK-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-GI-NEXT: tst w11, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <2 x float> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
@@ -438,35 +884,70 @@ entry:
}
define <2 x i64> @utest_f32i64(<2 x float> %x) {
-; CHECK-LABEL: utest_f32i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov s0, v0.s[1]
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utest_f32i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: mov s0, v0.s[1]
+; CHECK-SD-NEXT: bl __fixunssfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-SD-NEXT: bl __fixunssfti
+; CHECK-SD-NEXT: cmp x1, #0
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-SD-NEXT: cmp x20, #0
+; CHECK-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utest_f32i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov s8, v0.s[1]
+; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-GI-NEXT: bl __fixunssfti
+; CHECK-GI-NEXT: fmov s0, s8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixunssfti
+; CHECK-GI-NEXT: cmp x20, #1
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lo
+; CHECK-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-GI-NEXT: cmp x1, #1
+; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptoui <2 x float> %x to <2 x i128>
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -476,43 +957,94 @@ entry:
}
define <2 x i64> @ustest_f32i64(<2 x float> %x) {
-; CHECK-LABEL: ustest_f32i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov s0, v0.s[1]
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csinc x8, x1, xzr, lt
-; CHECK-NEXT: csel x9, x0, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csel x10, x19, xzr, lt
-; CHECK-NEXT: csinc x11, x20, xzr, lt
-; CHECK-NEXT: cmp xzr, x10
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ngcs xzr, x11
-; CHECK-NEXT: csel x10, x10, xzr, lt
-; CHECK-NEXT: cmp xzr, x9
-; CHECK-NEXT: ngcs xzr, x8
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: csel x8, x9, xzr, lt
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ustest_f32i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-SD-NEXT: bl __fixsfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: mov s0, v0.s[1]
+; CHECK-SD-NEXT: bl __fixsfti
+; CHECK-SD-NEXT: cmp x1, #1
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csinc x8, x1, xzr, lt
+; CHECK-SD-NEXT: csel x9, x0, xzr, lt
+; CHECK-SD-NEXT: cmp x20, #1
+; CHECK-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-SD-NEXT: csinc x11, x20, xzr, lt
+; CHECK-SD-NEXT: cmp xzr, x10
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ngcs xzr, x11
+; CHECK-SD-NEXT: csel x10, x10, xzr, lt
+; CHECK-SD-NEXT: cmp xzr, x9
+; CHECK-SD-NEXT: ngcs xzr, x8
+; CHECK-SD-NEXT: fmov d0, x10
+; CHECK-SD-NEXT: csel x8, x9, xzr, lt
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ustest_f32i64:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov s8, v0.s[1]
+; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-GI-NEXT: bl __fixsfti
+; CHECK-GI-NEXT: fmov s0, s8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixsfti
+; CHECK-GI-NEXT: cmp x20, #1
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lt
+; CHECK-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-GI-NEXT: cmp x1, #1
+; CHECK-GI-NEXT: cset w9, lt
+; CHECK-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-GI-NEXT: cmp x8, #0
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: cset w10, gt
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-GI-NEXT: cmp x9, #0
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: cset w11, gt
+; CHECK-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-GI-NEXT: tst w11, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <2 x float> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -524,27 +1056,121 @@ entry:
}
define <2 x i64> @stest_f16i64(<2 x half> %x) {
-; CHECK-CVT-LABEL: stest_f16i64:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-CVT-NEXT: fcvt s0, h0
-; CHECK-CVT-NEXT: fcvt s1, h1
-; CHECK-CVT-NEXT: fcvtzs x8, s0
-; CHECK-CVT-NEXT: fcvtzs x9, s1
-; CHECK-CVT-NEXT: fmov d0, x8
-; CHECK-CVT-NEXT: mov v0.d[1], x9
-; CHECK-CVT-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f16i64:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-SD-NEXT: fcvt s0, h0
+; CHECK-CVT-SD-NEXT: fcvt s1, h1
+; CHECK-CVT-SD-NEXT: fcvtzs x8, s0
+; CHECK-CVT-SD-NEXT: fcvtzs x9, s1
+; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: mov v0.d[1], x9
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i64:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-SD-NEXT: fcvtzs x8, h0
+; CHECK-FP16-SD-NEXT: fcvtzs x9, h1
+; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: mov v0.d[1], x9
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-CVT-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzs x9, s0
+; CHECK-CVT-GI-NEXT: fcvtzs x10, s1
+; CHECK-CVT-GI-NEXT: asr x11, x9, #63
+; CHECK-CVT-GI-NEXT: cmp x9, x8
+; CHECK-CVT-GI-NEXT: cset w12, lo
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: asr x13, x10, #63
+; CHECK-CVT-GI-NEXT: cset w14, lt
+; CHECK-CVT-GI-NEXT: csel w12, w12, w14, eq
+; CHECK-CVT-GI-NEXT: cmp x10, x8
+; CHECK-CVT-GI-NEXT: cset w14, lo
+; CHECK-CVT-GI-NEXT: cmp x13, #0
+; CHECK-CVT-GI-NEXT: cset w15, lt
+; CHECK-CVT-GI-NEXT: csel w14, w14, w15, eq
+; CHECK-CVT-GI-NEXT: tst w12, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, x8, ne
+; CHECK-CVT-GI-NEXT: csel x11, x11, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w14, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x10, x8, ne
+; CHECK-CVT-GI-NEXT: csel x10, x13, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x9, x16
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w13, ge
+; CHECK-CVT-GI-NEXT: cmn x11, #1
+; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-CVT-GI-NEXT: cmp x8, x16
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w13, ge
+; CHECK-CVT-GI-NEXT: cmn x10, #1
+; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, x16, ne
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x9
+; CHECK-CVT-GI-NEXT: csel x8, x8, x16, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x8
+; CHECK-CVT-GI-NEXT: ret
;
-; CHECK-FP16-LABEL: stest_f16i64:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-NEXT: fcvtzs x8, h0
-; CHECK-FP16-NEXT: fcvtzs x9, h1
-; CHECK-FP16-NEXT: fmov d0, x8
-; CHECK-FP16-NEXT: mov v0.d[1], x9
-; CHECK-FP16-NEXT: ret
+; CHECK-FP16-GI-LABEL: stest_f16i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzs x9, h0
+; CHECK-FP16-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-FP16-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
+; CHECK-FP16-GI-NEXT: fcvtzs x10, h1
+; CHECK-FP16-GI-NEXT: asr x11, x9, #63
+; CHECK-FP16-GI-NEXT: cmp x9, x8
+; CHECK-FP16-GI-NEXT: cset w12, lo
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w14, lt
+; CHECK-FP16-GI-NEXT: asr x13, x10, #63
+; CHECK-FP16-GI-NEXT: csel w12, w12, w14, eq
+; CHECK-FP16-GI-NEXT: cmp x10, x8
+; CHECK-FP16-GI-NEXT: cset w14, lo
+; CHECK-FP16-GI-NEXT: cmp x13, #0
+; CHECK-FP16-GI-NEXT: cset w15, lt
+; CHECK-FP16-GI-NEXT: csel w14, w14, w15, eq
+; CHECK-FP16-GI-NEXT: tst w12, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, x8, ne
+; CHECK-FP16-GI-NEXT: csel x11, x11, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w14, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x10, x8, ne
+; CHECK-FP16-GI-NEXT: csel x10, x13, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x9, x16
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w13, ge
+; CHECK-FP16-GI-NEXT: cmn x11, #1
+; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-FP16-GI-NEXT: cmp x8, x16
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w13, ge
+; CHECK-FP16-GI-NEXT: cmn x10, #1
+; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, x16, ne
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x9
+; CHECK-FP16-GI-NEXT: csel x8, x8, x16, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x8
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 9223372036854775807, i128 9223372036854775807>
@@ -556,35 +1182,57 @@ entry:
}
define <2 x i64> @utesth_f16i64(<2 x half> %x) {
-; CHECK-LABEL: utesth_f16i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov h0, v0.h[1]
-; CHECK-NEXT: bl __fixunshfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
-; CHECK-NEXT: bl __fixunshfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utesth_f16i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: mov h0, v0.h[1]
+; CHECK-SD-NEXT: bl __fixunshfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-SD-NEXT: bl __fixunshfti
+; CHECK-SD-NEXT: cmp x1, #0
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-SD-NEXT: cmp x20, #0
+; CHECK-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzu x8, s0
+; CHECK-CVT-GI-NEXT: fcvtzu x9, s1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzu x8, h0
+; CHECK-FP16-GI-NEXT: fcvtzu x9, h1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <2 x half> %x to <2 x i128>
%0 = icmp ult <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -594,43 +1242,121 @@ entry:
}
define <2 x i64> @ustest_f16i64(<2 x half> %x) {
-; CHECK-LABEL: ustest_f16i64:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
-; CHECK-NEXT: bl __fixhfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov h0, v0.h[1]
-; CHECK-NEXT: bl __fixhfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csinc x8, x1, xzr, lt
-; CHECK-NEXT: csel x9, x0, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csel x10, x19, xzr, lt
-; CHECK-NEXT: csinc x11, x20, xzr, lt
-; CHECK-NEXT: cmp xzr, x10
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ngcs xzr, x11
-; CHECK-NEXT: csel x10, x10, xzr, lt
-; CHECK-NEXT: cmp xzr, x9
-; CHECK-NEXT: ngcs xzr, x8
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: csel x8, x9, xzr, lt
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ustest_f16i64:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-SD-NEXT: bl __fixhfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: mov h0, v0.h[1]
+; CHECK-SD-NEXT: bl __fixhfti
+; CHECK-SD-NEXT: cmp x1, #1
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csinc x8, x1, xzr, lt
+; CHECK-SD-NEXT: csel x9, x0, xzr, lt
+; CHECK-SD-NEXT: cmp x20, #1
+; CHECK-SD-NEXT: csel x10, x19, xzr, lt
+; CHECK-SD-NEXT: csinc x11, x20, xzr, lt
+; CHECK-SD-NEXT: cmp xzr, x10
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: ngcs xzr, x11
+; CHECK-SD-NEXT: csel x10, x10, xzr, lt
+; CHECK-SD-NEXT: cmp xzr, x9
+; CHECK-SD-NEXT: ngcs xzr, x8
+; CHECK-SD-NEXT: fmov d0, x10
+; CHECK-SD-NEXT: csel x8, x9, xzr, lt
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i64:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzs x8, s0
+; CHECK-CVT-GI-NEXT: fcvtzs x9, s1
+; CHECK-CVT-GI-NEXT: asr x10, x8, #63
+; CHECK-CVT-GI-NEXT: cmp x10, #1
+; CHECK-CVT-GI-NEXT: asr x11, x9, #63
+; CHECK-CVT-GI-NEXT: cset w12, lt
+; CHECK-CVT-GI-NEXT: csel w12, wzr, w12, eq
+; CHECK-CVT-GI-NEXT: cmp x11, #1
+; CHECK-CVT-GI-NEXT: cset w13, lt
+; CHECK-CVT-GI-NEXT: csel w13, wzr, w13, eq
+; CHECK-CVT-GI-NEXT: tst w12, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x10, x10, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w13, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x11, x11, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w10, gt
+; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-CVT-GI-NEXT: cmp x9, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w11, gt
+; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i64:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzs x8, h0
+; CHECK-FP16-GI-NEXT: fcvtzs x9, h1
+; CHECK-FP16-GI-NEXT: asr x10, x8, #63
+; CHECK-FP16-GI-NEXT: cmp x10, #1
+; CHECK-FP16-GI-NEXT: cset w12, lt
+; CHECK-FP16-GI-NEXT: asr x11, x9, #63
+; CHECK-FP16-GI-NEXT: csel w12, wzr, w12, eq
+; CHECK-FP16-GI-NEXT: cmp x11, #1
+; CHECK-FP16-GI-NEXT: cset w13, lt
+; CHECK-FP16-GI-NEXT: csel w13, wzr, w13, eq
+; CHECK-FP16-GI-NEXT: tst w12, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x10, x10, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w13, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x11, x11, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w10, gt
+; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-FP16-GI-NEXT: cmp x9, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w11, gt
+; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
%0 = icmp slt <2 x i128> %conv, <i128 18446744073709551616, i128 18446744073709551616>
@@ -660,15 +1386,24 @@ entry:
}
define <2 x i32> @utest_f64i32_mm(<2 x double> %x) {
-; CHECK-LABEL: utest_f64i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov d1, v0.d[1]
-; CHECK-NEXT: fcvtzu w8, d0
-; CHECK-NEXT: fcvtzu w9, d1
-; CHECK-NEXT: fmov s0, w8
-; CHECK-NEXT: mov v0.s[1], w9
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utest_f64i32_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov d1, v0.d[1]
+; CHECK-SD-NEXT: fcvtzu w8, d0
+; CHECK-SD-NEXT: fcvtzu w9, d1
+; CHECK-SD-NEXT: fmov s0, w8
+; CHECK-SD-NEXT: mov v0.s[1], w9
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utest_f64i32_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-GI-NEXT: cmhi v2.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: ret
entry:
%conv = fptoui <2 x double> %x to <2 x i64>
%spec.store.select = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %conv, <2 x i64> <i64 4294967295, i64 4294967295>)
@@ -691,10 +1426,31 @@ entry:
}
define <4 x i32> @stest_f32i32_mm(<4 x float> %x) {
-; CHECK-LABEL: stest_f32i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stest_f32i32_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stest_f32i32_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-GI-NEXT: adrp x8, .LCPI30_1
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI30_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI30_0
+; CHECK-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI30_0]
+; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
@@ -704,10 +1460,24 @@ entry:
}
define <4 x i32> @utest_f32i32_mm(<4 x float> %x) {
-; CHECK-LABEL: utest_f32i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utest_f32i32_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utest_f32i32_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptoui <4 x float> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
@@ -716,10 +1486,28 @@ entry:
}
define <4 x i32> @ustest_f32i32_mm(<4 x float> %x) {
-; CHECK-LABEL: ustest_f32i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ustest_f32i32_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ustest_f32i32_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <4 x float> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
@@ -729,11 +1517,62 @@ entry:
}
define <4 x i32> @stest_f16i32_mm(<4 x half> %x) {
-; CHECK-LABEL: stest_f16i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stest_f16i32_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI33_1
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_1]
+; CHECK-CVT-GI-NEXT: adrp x8, .LCPI33_0
+; CHECK-CVT-GI-NEXT: fcvtl v1.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v1.2d, v1.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v2.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_0]
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d
+; CHECK-CVT-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v2.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: stest_f16i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[2]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI33_1
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: fcvt d1, h1
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-FP16-GI-NEXT: mov v2.d[1], v3.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_1]
+; CHECK-FP16-GI-NEXT: adrp x8, .LCPI33_0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v2.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v2.2d, v1.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: ldr q2, [x8, :lo12:.LCPI33_0]
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v0.2d, v2.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v2.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bif v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 2147483647, i64 2147483647, i64 2147483647, i64 2147483647>)
@@ -743,11 +1582,48 @@ entry:
}
define <4 x i32> @utesth_f16i32_mm(<4 x half> %x) {
-; CHECK-LABEL: utesth_f16i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utesth_f16i32_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzu v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmhi v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmhi v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v2.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzu v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzu v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmhi v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmhi v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <4 x half> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.umin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
@@ -756,11 +1632,56 @@ entry:
}
define <4 x i32> @ustest_f16i32_mm(<4 x half> %x) {
-; CHECK-LABEL: ustest_f16i32_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ustest_f16i32_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i32_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: fcvtl v0.4s, v0.4h
+; CHECK-CVT-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-CVT-GI-NEXT: fcvtl v2.2d, v0.2s
+; CHECK-CVT-GI-NEXT: fcvtl2 v0.2d, v0.4s
+; CHECK-CVT-GI-NEXT: fcvtzs v2.2d, v2.2d
+; CHECK-CVT-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-CVT-GI-NEXT: cmgt v4.2d, v1.2d, v0.2d
+; CHECK-CVT-GI-NEXT: bif v2.16b, v1.16b, v3.16b
+; CHECK-CVT-GI-NEXT: bif v0.16b, v1.16b, v4.16b
+; CHECK-CVT-GI-NEXT: cmgt v1.2d, v2.2d, #0
+; CHECK-CVT-GI-NEXT: cmgt v3.2d, v0.2d, #0
+; CHECK-CVT-GI-NEXT: and v1.16b, v2.16b, v1.16b
+; CHECK-CVT-GI-NEXT: and v0.16b, v0.16b, v3.16b
+; CHECK-CVT-GI-NEXT: uzp1 v0.4s, v1.4s, v0.4s
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i32_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h2, v0.h[1]
+; CHECK-FP16-GI-NEXT: mov h3, v0.h[2]
+; CHECK-FP16-GI-NEXT: mov h4, v0.h[3]
+; CHECK-FP16-GI-NEXT: fcvt d0, h0
+; CHECK-FP16-GI-NEXT: movi v1.2d, #0x000000ffffffff
+; CHECK-FP16-GI-NEXT: fcvt d2, h2
+; CHECK-FP16-GI-NEXT: fcvt d3, h3
+; CHECK-FP16-GI-NEXT: fcvt d4, h4
+; CHECK-FP16-GI-NEXT: mov v0.d[1], v2.d[0]
+; CHECK-FP16-GI-NEXT: mov v3.d[1], v4.d[0]
+; CHECK-FP16-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-FP16-GI-NEXT: fcvtzs v2.2d, v3.2d
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, v0.2d
+; CHECK-FP16-GI-NEXT: cmgt v4.2d, v1.2d, v2.2d
+; CHECK-FP16-GI-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: bit v1.16b, v2.16b, v4.16b
+; CHECK-FP16-GI-NEXT: cmgt v2.2d, v0.2d, #0
+; CHECK-FP16-GI-NEXT: cmgt v3.2d, v1.2d, #0
+; CHECK-FP16-GI-NEXT: and v0.16b, v0.16b, v2.16b
+; CHECK-FP16-GI-NEXT: and v1.16b, v1.16b, v3.16b
+; CHECK-FP16-GI-NEXT: uzp1 v0.4s, v0.4s, v1.4s
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <4 x half> %x to <4 x i64>
%spec.store.select = call <4 x i64> @llvm.smin.v4i64(<4 x i64> %conv, <4 x i64> <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>)
@@ -772,15 +1693,25 @@ entry:
; i16 saturate
define <2 x i16> @stest_f64i16_mm(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i16_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: movi v1.2s, #127, msl #8
-; CHECK-NEXT: xtn v0.2s, v0.2d
-; CHECK-NEXT: smin v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: mvni v1.2s, #127, msl #8
-; CHECK-NEXT: smax v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stest_f64i16_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: movi v1.2s, #127, msl #8
+; CHECK-SD-NEXT: xtn v0.2s, v0.2d
+; CHECK-SD-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: mvni v1.2s, #127, msl #8
+; CHECK-SD-NEXT: smax v0.2s, v0.2s, v1.2s
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stest_f64i16_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-GI-NEXT: movi v1.2s, #127, msl #8
+; CHECK-GI-NEXT: mvni v2.2s, #127, msl #8
+; CHECK-GI-NEXT: xtn v0.2s, v0.2d
+; CHECK-GI-NEXT: smin v0.2s, v0.2s, v1.2s
+; CHECK-GI-NEXT: smax v0.2s, v0.2s, v2.2s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i32>
%spec.store.select = call <2 x i32> @llvm.smin.v2i32(<2 x i32> %conv, <2 x i32> <i32 32767, i32 32767>)
@@ -864,20 +1795,30 @@ entry:
}
define <8 x i16> @stest_f16i16_mm(<8 x half> %x) {
-; CHECK-CVT-LABEL: stest_f16i16_mm:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-NEXT: sqxtn v0.4h, v1.4s
-; CHECK-CVT-NEXT: sqxtn2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f16i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: sqxtn2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzs v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-FP16-LABEL: stest_f16i16_mm:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-GI-LABEL: stest_f16i16_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-GI-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-GI-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-GI-NEXT: sqxtn2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
%spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767, i32 32767>)
@@ -887,20 +1828,30 @@ entry:
}
define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
-; CHECK-CVT-LABEL: utesth_f16i16_mm:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzu v2.4s, v0.4s
-; CHECK-CVT-NEXT: uqxtn v0.4h, v1.4s
-; CHECK-CVT-NEXT: uqxtn2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
+; CHECK-CVT-SD-LABEL: utesth_f16i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: uqxtn2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: utesth_f16i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
;
-; CHECK-FP16-LABEL: utesth_f16i16_mm:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-GI-LABEL: utesth_f16i16_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-GI-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-GI-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-GI-NEXT: uqxtn2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptoui <8 x half> %x to <8 x i32>
%spec.store.select = call <8 x i32> @llvm.umin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -909,20 +1860,30 @@ entry:
}
define <8 x i16> @ustest_f16i16_mm(<8 x half> %x) {
-; CHECK-CVT-LABEL: ustest_f16i16_mm:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: fcvtl v1.4s, v0.4h
-; CHECK-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-CVT-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-CVT-NEXT: fcvtzs v2.4s, v0.4s
-; CHECK-CVT-NEXT: sqxtun v0.4h, v1.4s
-; CHECK-CVT-NEXT: sqxtun2 v0.8h, v2.4s
-; CHECK-CVT-NEXT: ret
+; CHECK-CVT-SD-LABEL: ustest_f16i16_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-CVT-SD-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-CVT-SD-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-CVT-SD-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-CVT-SD-NEXT: sqxtun v0.4h, v1.4s
+; CHECK-CVT-SD-NEXT: sqxtun2 v0.8h, v2.4s
+; CHECK-CVT-SD-NEXT: ret
;
-; CHECK-FP16-LABEL: ustest_f16i16_mm:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-FP16-NEXT: ret
+; CHECK-FP16-SD-LABEL: ustest_f16i16_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: fcvtzu v0.8h, v0.8h
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ustest_f16i16_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: fcvtl v1.4s, v0.4h
+; CHECK-GI-NEXT: fcvtl2 v0.4s, v0.8h
+; CHECK-GI-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-GI-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-GI-NEXT: sqxtun v0.4h, v1.4s
+; CHECK-GI-NEXT: sqxtun2 v0.8h, v2.4s
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <8 x half> %x to <8 x i32>
%spec.store.select = call <8 x i32> @llvm.smin.v8i32(<8 x i32> %conv, <8 x i32> <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>)
@@ -934,10 +1895,72 @@ entry:
; i64 saturate
define <2 x i64> @stest_f64i64_mm(<2 x double> %x) {
-; CHECK-LABEL: stest_f64i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stest_f64i64_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stest_f64i64_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w21, -24
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w30, -40
+; CHECK-GI-NEXT: .cfi_offset b8, -48
+; CHECK-GI-NEXT: mov d8, v0.d[1]
+; CHECK-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: bl __fixdfti
+; CHECK-GI-NEXT: fmov d0, d8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixdfti
+; CHECK-GI-NEXT: cmp x19, x21
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lo
+; CHECK-GI-NEXT: cmp x20, #0
+; CHECK-GI-NEXT: cset w9, lt
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-GI-NEXT: cmp x0, x21
+; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: cmp x1, #0
+; CHECK-GI-NEXT: cset w10, lt
+; CHECK-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-GI-NEXT: cmp x8, x22
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: cset w13, ge
+; CHECK-GI-NEXT: cmn x10, #1
+; CHECK-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-GI-NEXT: cmp x9, x22
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: cset w13, ge
+; CHECK-GI-NEXT: cmn x11, #1
+; CHECK-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-GI-NEXT: tst w11, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
@@ -947,34 +1970,68 @@ entry:
}
define <2 x i64> @utest_f64i64_mm(<2 x double> %x) {
-; CHECK-LABEL: utest_f64i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov d0, v0.d[1]
-; CHECK-NEXT: bl __fixunsdfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: bl __fixunsdfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utest_f64i64_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: mov d0, v0.d[1]
+; CHECK-SD-NEXT: bl __fixunsdfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: bl __fixunsdfti
+; CHECK-SD-NEXT: cmp x1, #0
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-SD-NEXT: cmp x20, #0
+; CHECK-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utest_f64i64_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: mov d8, v0.d[1]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: bl __fixunsdfti
+; CHECK-GI-NEXT: fmov d0, d8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixunsdfti
+; CHECK-GI-NEXT: cmp x20, #1
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lo
+; CHECK-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-GI-NEXT: cmp x1, #1
+; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptoui <2 x double> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -983,40 +2040,90 @@ entry:
}
define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) {
-; CHECK-LABEL: ustest_f64i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0
-; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov d0, v0.d[1]
-; CHECK-NEXT: bl __fixdfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, lt
-; CHECK-NEXT: csinc x9, x1, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csinc x10, x20, xzr, lt
-; CHECK-NEXT: csel x11, x19, xzr, lt
-; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: csel x10, xzr, x11, lt
-; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: csel x8, xzr, x8, lt
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ustest_f64i64_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-SD-NEXT: bl __fixdfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: mov d0, v0.d[1]
+; CHECK-SD-NEXT: bl __fixdfti
+; CHECK-SD-NEXT: cmp x1, #1
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-SD-NEXT: cmp x20, #1
+; CHECK-SD-NEXT: csinc x10, x20, xzr, lt
+; CHECK-SD-NEXT: csel x11, x19, xzr, lt
+; CHECK-SD-NEXT: cmp x10, #0
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: csel x10, xzr, x11, lt
+; CHECK-SD-NEXT: cmp x9, #0
+; CHECK-SD-NEXT: csel x8, xzr, x8, lt
+; CHECK-SD-NEXT: fmov d0, x10
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ustest_f64i64_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: mov d8, v0.d[1]
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: bl __fixdfti
+; CHECK-GI-NEXT: fmov d0, d8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixdfti
+; CHECK-GI-NEXT: cmp x20, #1
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lt
+; CHECK-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-GI-NEXT: cmp x1, #1
+; CHECK-GI-NEXT: cset w9, lt
+; CHECK-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-GI-NEXT: cmp x8, #0
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: cset w10, gt
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-GI-NEXT: cmp x9, #0
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: cset w11, gt
+; CHECK-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-GI-NEXT: tst w11, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <2 x double> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -1026,11 +2133,74 @@ entry:
}
define <2 x i64> @stest_f32i64_mm(<2 x float> %x) {
-; CHECK-LABEL: stest_f32i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: fcvtl v0.2d, v0.2s
-; CHECK-NEXT: fcvtzs v0.2d, v0.2d
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: stest_f32i64_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: fcvtl v0.2d, v0.2s
+; CHECK-SD-NEXT: fcvtzs v0.2d, v0.2d
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: stest_f32i64_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-48]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x22, x21, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 48
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w21, -24
+; CHECK-GI-NEXT: .cfi_offset w22, -32
+; CHECK-GI-NEXT: .cfi_offset w30, -40
+; CHECK-GI-NEXT: .cfi_offset b8, -48
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov s8, v0.s[1]
+; CHECK-GI-NEXT: mov x21, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-GI-NEXT: mov x22, #-9223372036854775808 // =0x8000000000000000
+; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-GI-NEXT: bl __fixsfti
+; CHECK-GI-NEXT: fmov s0, s8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixsfti
+; CHECK-GI-NEXT: cmp x19, x21
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lo
+; CHECK-GI-NEXT: cmp x20, #0
+; CHECK-GI-NEXT: cset w9, lt
+; CHECK-GI-NEXT: csel w8, w8, w9, eq
+; CHECK-GI-NEXT: cmp x0, x21
+; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: cmp x1, #0
+; CHECK-GI-NEXT: cset w10, lt
+; CHECK-GI-NEXT: csel w9, w9, w10, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, x21, ne
+; CHECK-GI-NEXT: csel x10, x20, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: csel x9, x0, x21, ne
+; CHECK-GI-NEXT: csel x11, x1, xzr, ne
+; CHECK-GI-NEXT: cmp x8, x22
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: cset w13, ge
+; CHECK-GI-NEXT: cmn x10, #1
+; CHECK-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-GI-NEXT: cmp x9, x22
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: cset w13, ge
+; CHECK-GI-NEXT: cmn x11, #1
+; CHECK-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x8, x8, x22, ne
+; CHECK-GI-NEXT: tst w11, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: csel x9, x9, x22, ne
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-GI-NEXT: ldp x22, x21, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #48 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <2 x float> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
@@ -1040,35 +2210,70 @@ entry:
}
define <2 x i64> @utest_f32i64_mm(<2 x float> %x) {
-; CHECK-LABEL: utest_f32i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov s0, v0.s[1]
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: bl __fixunssfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utest_f32i64_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: mov s0, v0.s[1]
+; CHECK-SD-NEXT: bl __fixunssfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-SD-NEXT: bl __fixunssfti
+; CHECK-SD-NEXT: cmp x1, #0
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-SD-NEXT: cmp x20, #0
+; CHECK-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: utest_f32i64_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov s8, v0.s[1]
+; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-GI-NEXT: bl __fixunssfti
+; CHECK-GI-NEXT: fmov s0, s8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixunssfti
+; CHECK-GI-NEXT: cmp x20, #1
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lo
+; CHECK-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-GI-NEXT: cmp x1, #1
+; CHECK-GI-NEXT: cset w9, lo
+; CHECK-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptoui <2 x float> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -1077,41 +2282,92 @@ entry:
}
define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) {
-; CHECK-LABEL: ustest_f32i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $s0 killed $s0 killed $q0
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov s0, v0.s[1]
-; CHECK-NEXT: bl __fixsfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, lt
-; CHECK-NEXT: csinc x9, x1, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csinc x10, x20, xzr, lt
-; CHECK-NEXT: csel x11, x19, xzr, lt
-; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: csel x10, xzr, x11, lt
-; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: csel x8, xzr, x8, lt
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ustest_f32i64_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-SD-NEXT: bl __fixsfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: mov s0, v0.s[1]
+; CHECK-SD-NEXT: bl __fixsfti
+; CHECK-SD-NEXT: cmp x1, #1
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-SD-NEXT: cmp x20, #1
+; CHECK-SD-NEXT: csinc x10, x20, xzr, lt
+; CHECK-SD-NEXT: csel x11, x19, xzr, lt
+; CHECK-SD-NEXT: cmp x10, #0
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: csel x10, xzr, x11, lt
+; CHECK-SD-NEXT: cmp x9, #0
+; CHECK-SD-NEXT: csel x8, xzr, x8, lt
+; CHECK-SD-NEXT: fmov d0, x10
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: ustest_f32i64_mm:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: str d8, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-GI-NEXT: str x30, [sp, #8] // 8-byte Folded Spill
+; CHECK-GI-NEXT: stp x20, x19, [sp, #16] // 16-byte Folded Spill
+; CHECK-GI-NEXT: .cfi_def_cfa_offset 32
+; CHECK-GI-NEXT: .cfi_offset w19, -8
+; CHECK-GI-NEXT: .cfi_offset w20, -16
+; CHECK-GI-NEXT: .cfi_offset w30, -24
+; CHECK-GI-NEXT: .cfi_offset b8, -32
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov s8, v0.s[1]
+; CHECK-GI-NEXT: // kill: def $s0 killed $s0 killed $q0
+; CHECK-GI-NEXT: bl __fixsfti
+; CHECK-GI-NEXT: fmov s0, s8
+; CHECK-GI-NEXT: mov x19, x0
+; CHECK-GI-NEXT: mov x20, x1
+; CHECK-GI-NEXT: bl __fixsfti
+; CHECK-GI-NEXT: cmp x20, #1
+; CHECK-GI-NEXT: ldr x30, [sp, #8] // 8-byte Folded Reload
+; CHECK-GI-NEXT: cset w8, lt
+; CHECK-GI-NEXT: csel w8, wzr, w8, eq
+; CHECK-GI-NEXT: cmp x1, #1
+; CHECK-GI-NEXT: cset w9, lt
+; CHECK-GI-NEXT: csel w9, wzr, w9, eq
+; CHECK-GI-NEXT: tst w8, #0x1
+; CHECK-GI-NEXT: csel x8, x19, xzr, ne
+; CHECK-GI-NEXT: csinc x10, x20, xzr, ne
+; CHECK-GI-NEXT: tst w9, #0x1
+; CHECK-GI-NEXT: csel x9, x0, xzr, ne
+; CHECK-GI-NEXT: csinc x11, x1, xzr, ne
+; CHECK-GI-NEXT: cmp x8, #0
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x10, #0
+; CHECK-GI-NEXT: cset w10, gt
+; CHECK-GI-NEXT: ldp x20, x19, [sp, #16] // 16-byte Folded Reload
+; CHECK-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-GI-NEXT: cmp x9, #0
+; CHECK-GI-NEXT: cset w12, hi
+; CHECK-GI-NEXT: cmp x11, #0
+; CHECK-GI-NEXT: cset w11, gt
+; CHECK-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-GI-NEXT: tst w10, #0x1
+; CHECK-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-GI-NEXT: tst w11, #0x1
+; CHECK-GI-NEXT: fmov d0, x8
+; CHECK-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-GI-NEXT: mov v0.d[1], x9
+; CHECK-GI-NEXT: ldr d8, [sp], #32 // 8-byte Folded Reload
+; CHECK-GI-NEXT: ret
entry:
%conv = fptosi <2 x float> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -1121,27 +2377,121 @@ entry:
}
define <2 x i64> @stest_f16i64_mm(<2 x half> %x) {
-; CHECK-CVT-LABEL: stest_f16i64_mm:
-; CHECK-CVT: // %bb.0: // %entry
-; CHECK-CVT-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-CVT-NEXT: mov h1, v0.h[1]
-; CHECK-CVT-NEXT: fcvt s0, h0
-; CHECK-CVT-NEXT: fcvt s1, h1
-; CHECK-CVT-NEXT: fcvtzs x8, s0
-; CHECK-CVT-NEXT: fcvtzs x9, s1
-; CHECK-CVT-NEXT: fmov d0, x8
-; CHECK-CVT-NEXT: mov v0.d[1], x9
-; CHECK-CVT-NEXT: ret
+; CHECK-CVT-SD-LABEL: stest_f16i64_mm:
+; CHECK-CVT-SD: // %bb.0: // %entry
+; CHECK-CVT-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-SD-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-SD-NEXT: fcvt s0, h0
+; CHECK-CVT-SD-NEXT: fcvt s1, h1
+; CHECK-CVT-SD-NEXT: fcvtzs x8, s0
+; CHECK-CVT-SD-NEXT: fcvtzs x9, s1
+; CHECK-CVT-SD-NEXT: fmov d0, x8
+; CHECK-CVT-SD-NEXT: mov v0.d[1], x9
+; CHECK-CVT-SD-NEXT: ret
+;
+; CHECK-FP16-SD-LABEL: stest_f16i64_mm:
+; CHECK-FP16-SD: // %bb.0: // %entry
+; CHECK-FP16-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-SD-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-SD-NEXT: fcvtzs x8, h0
+; CHECK-FP16-SD-NEXT: fcvtzs x9, h1
+; CHECK-FP16-SD-NEXT: fmov d0, x8
+; CHECK-FP16-SD-NEXT: mov v0.d[1], x9
+; CHECK-FP16-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: stest_f16i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-CVT-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzs x9, s0
+; CHECK-CVT-GI-NEXT: fcvtzs x10, s1
+; CHECK-CVT-GI-NEXT: asr x11, x9, #63
+; CHECK-CVT-GI-NEXT: cmp x9, x8
+; CHECK-CVT-GI-NEXT: cset w12, lo
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: asr x13, x10, #63
+; CHECK-CVT-GI-NEXT: cset w14, lt
+; CHECK-CVT-GI-NEXT: csel w12, w12, w14, eq
+; CHECK-CVT-GI-NEXT: cmp x10, x8
+; CHECK-CVT-GI-NEXT: cset w14, lo
+; CHECK-CVT-GI-NEXT: cmp x13, #0
+; CHECK-CVT-GI-NEXT: cset w15, lt
+; CHECK-CVT-GI-NEXT: csel w14, w14, w15, eq
+; CHECK-CVT-GI-NEXT: tst w12, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, x8, ne
+; CHECK-CVT-GI-NEXT: csel x11, x11, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w14, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x10, x8, ne
+; CHECK-CVT-GI-NEXT: csel x10, x13, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x9, x16
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w13, ge
+; CHECK-CVT-GI-NEXT: cmn x11, #1
+; CHECK-CVT-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-CVT-GI-NEXT: cmp x8, x16
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w13, ge
+; CHECK-CVT-GI-NEXT: cmn x10, #1
+; CHECK-CVT-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, x16, ne
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x9
+; CHECK-CVT-GI-NEXT: csel x8, x8, x16, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x8
+; CHECK-CVT-GI-NEXT: ret
;
-; CHECK-FP16-LABEL: stest_f16i64_mm:
-; CHECK-FP16: // %bb.0: // %entry
-; CHECK-FP16-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-FP16-NEXT: mov h1, v0.h[1]
-; CHECK-FP16-NEXT: fcvtzs x8, h0
-; CHECK-FP16-NEXT: fcvtzs x9, h1
-; CHECK-FP16-NEXT: fmov d0, x8
-; CHECK-FP16-NEXT: mov v0.d[1], x9
-; CHECK-FP16-NEXT: ret
+; CHECK-FP16-GI-LABEL: stest_f16i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzs x9, h0
+; CHECK-FP16-GI-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff
+; CHECK-FP16-GI-NEXT: mov x16, #-9223372036854775808 // =0x8000000000000000
+; CHECK-FP16-GI-NEXT: fcvtzs x10, h1
+; CHECK-FP16-GI-NEXT: asr x11, x9, #63
+; CHECK-FP16-GI-NEXT: cmp x9, x8
+; CHECK-FP16-GI-NEXT: cset w12, lo
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w14, lt
+; CHECK-FP16-GI-NEXT: asr x13, x10, #63
+; CHECK-FP16-GI-NEXT: csel w12, w12, w14, eq
+; CHECK-FP16-GI-NEXT: cmp x10, x8
+; CHECK-FP16-GI-NEXT: cset w14, lo
+; CHECK-FP16-GI-NEXT: cmp x13, #0
+; CHECK-FP16-GI-NEXT: cset w15, lt
+; CHECK-FP16-GI-NEXT: csel w14, w14, w15, eq
+; CHECK-FP16-GI-NEXT: tst w12, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, x8, ne
+; CHECK-FP16-GI-NEXT: csel x11, x11, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w14, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x10, x8, ne
+; CHECK-FP16-GI-NEXT: csel x10, x13, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x9, x16
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w13, ge
+; CHECK-FP16-GI-NEXT: cmn x11, #1
+; CHECK-FP16-GI-NEXT: csel w11, w12, w13, eq
+; CHECK-FP16-GI-NEXT: cmp x8, x16
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w13, ge
+; CHECK-FP16-GI-NEXT: cmn x10, #1
+; CHECK-FP16-GI-NEXT: csel w10, w12, w13, eq
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, x16, ne
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x9
+; CHECK-FP16-GI-NEXT: csel x8, x8, x16, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x8
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 9223372036854775807, i128 9223372036854775807>)
@@ -1151,35 +2501,57 @@ entry:
}
define <2 x i64> @utesth_f16i64_mm(<2 x half> %x) {
-; CHECK-LABEL: utesth_f16i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: mov h0, v0.h[1]
-; CHECK-NEXT: bl __fixunshfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
-; CHECK-NEXT: bl __fixunshfti
-; CHECK-NEXT: cmp x1, #0
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, eq
-; CHECK-NEXT: cmp x20, #0
-; CHECK-NEXT: csel x9, x19, xzr, eq
-; CHECK-NEXT: fmov d0, x8
-; CHECK-NEXT: fmov d1, x9
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: utesth_f16i64_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: mov h0, v0.h[1]
+; CHECK-SD-NEXT: bl __fixunshfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-SD-NEXT: bl __fixunshfti
+; CHECK-SD-NEXT: cmp x1, #0
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csel x8, x0, xzr, eq
+; CHECK-SD-NEXT: cmp x20, #0
+; CHECK-SD-NEXT: csel x9, x19, xzr, eq
+; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: fmov d1, x9
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: utesth_f16i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzu x8, s0
+; CHECK-CVT-GI-NEXT: fcvtzu x9, s1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: utesth_f16i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzu x8, h0
+; CHECK-FP16-GI-NEXT: fcvtzu x9, h1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptoui <2 x half> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.umin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
@@ -1188,41 +2560,119 @@ entry:
}
define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) {
-; CHECK-LABEL: ustest_f16i64_mm:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
-; CHECK-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w19, -8
-; CHECK-NEXT: .cfi_offset w20, -16
-; CHECK-NEXT: .cfi_offset w30, -32
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: str q0, [sp] // 16-byte Folded Spill
-; CHECK-NEXT: // kill: def $h0 killed $h0 killed $q0
-; CHECK-NEXT: bl __fixhfti
-; CHECK-NEXT: ldr q0, [sp] // 16-byte Folded Reload
-; CHECK-NEXT: mov x19, x0
-; CHECK-NEXT: mov x20, x1
-; CHECK-NEXT: mov h0, v0.h[1]
-; CHECK-NEXT: bl __fixhfti
-; CHECK-NEXT: cmp x1, #1
-; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
-; CHECK-NEXT: csel x8, x0, xzr, lt
-; CHECK-NEXT: csinc x9, x1, xzr, lt
-; CHECK-NEXT: cmp x20, #1
-; CHECK-NEXT: csinc x10, x20, xzr, lt
-; CHECK-NEXT: csel x11, x19, xzr, lt
-; CHECK-NEXT: cmp x10, #0
-; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: csel x10, xzr, x11, lt
-; CHECK-NEXT: cmp x9, #0
-; CHECK-NEXT: csel x8, xzr, x8, lt
-; CHECK-NEXT: fmov d0, x10
-; CHECK-NEXT: fmov d1, x8
-; CHECK-NEXT: mov v0.d[1], v1.d[0]
-; CHECK-NEXT: add sp, sp, #48
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: ustest_f16i64_mm:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: sub sp, sp, #48
+; CHECK-SD-NEXT: str x30, [sp, #16] // 8-byte Folded Spill
+; CHECK-SD-NEXT: stp x20, x19, [sp, #32] // 16-byte Folded Spill
+; CHECK-SD-NEXT: .cfi_def_cfa_offset 48
+; CHECK-SD-NEXT: .cfi_offset w19, -8
+; CHECK-SD-NEXT: .cfi_offset w20, -16
+; CHECK-SD-NEXT: .cfi_offset w30, -32
+; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill
+; CHECK-SD-NEXT: // kill: def $h0 killed $h0 killed $q0
+; CHECK-SD-NEXT: bl __fixhfti
+; CHECK-SD-NEXT: ldr q0, [sp] // 16-byte Folded Reload
+; CHECK-SD-NEXT: mov x19, x0
+; CHECK-SD-NEXT: mov x20, x1
+; CHECK-SD-NEXT: mov h0, v0.h[1]
+; CHECK-SD-NEXT: bl __fixhfti
+; CHECK-SD-NEXT: cmp x1, #1
+; CHECK-SD-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload
+; CHECK-SD-NEXT: csel x8, x0, xzr, lt
+; CHECK-SD-NEXT: csinc x9, x1, xzr, lt
+; CHECK-SD-NEXT: cmp x20, #1
+; CHECK-SD-NEXT: csinc x10, x20, xzr, lt
+; CHECK-SD-NEXT: csel x11, x19, xzr, lt
+; CHECK-SD-NEXT: cmp x10, #0
+; CHECK-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
+; CHECK-SD-NEXT: csel x10, xzr, x11, lt
+; CHECK-SD-NEXT: cmp x9, #0
+; CHECK-SD-NEXT: csel x8, xzr, x8, lt
+; CHECK-SD-NEXT: fmov d0, x10
+; CHECK-SD-NEXT: fmov d1, x8
+; CHECK-SD-NEXT: mov v0.d[1], v1.d[0]
+; CHECK-SD-NEXT: add sp, sp, #48
+; CHECK-SD-NEXT: ret
+;
+; CHECK-CVT-GI-LABEL: ustest_f16i64_mm:
+; CHECK-CVT-GI: // %bb.0: // %entry
+; CHECK-CVT-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-CVT-GI-NEXT: mov h1, v0.h[1]
+; CHECK-CVT-GI-NEXT: fcvt s0, h0
+; CHECK-CVT-GI-NEXT: fcvt s1, h1
+; CHECK-CVT-GI-NEXT: fcvtzs x8, s0
+; CHECK-CVT-GI-NEXT: fcvtzs x9, s1
+; CHECK-CVT-GI-NEXT: asr x10, x8, #63
+; CHECK-CVT-GI-NEXT: cmp x10, #1
+; CHECK-CVT-GI-NEXT: asr x11, x9, #63
+; CHECK-CVT-GI-NEXT: cset w12, lt
+; CHECK-CVT-GI-NEXT: csel w12, wzr, w12, eq
+; CHECK-CVT-GI-NEXT: cmp x11, #1
+; CHECK-CVT-GI-NEXT: cset w13, lt
+; CHECK-CVT-GI-NEXT: csel w13, wzr, w13, eq
+; CHECK-CVT-GI-NEXT: tst w12, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x10, x10, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w13, #0x1
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: csinc x11, x11, xzr, ne
+; CHECK-CVT-GI-NEXT: cmp x8, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x10, #0
+; CHECK-CVT-GI-NEXT: cset w10, gt
+; CHECK-CVT-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-CVT-GI-NEXT: cmp x9, #0
+; CHECK-CVT-GI-NEXT: cset w12, hi
+; CHECK-CVT-GI-NEXT: cmp x11, #0
+; CHECK-CVT-GI-NEXT: cset w11, gt
+; CHECK-CVT-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-CVT-GI-NEXT: tst w10, #0x1
+; CHECK-CVT-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-CVT-GI-NEXT: tst w11, #0x1
+; CHECK-CVT-GI-NEXT: fmov d0, x8
+; CHECK-CVT-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-CVT-GI-NEXT: mov v0.d[1], x9
+; CHECK-CVT-GI-NEXT: ret
+;
+; CHECK-FP16-GI-LABEL: ustest_f16i64_mm:
+; CHECK-FP16-GI: // %bb.0: // %entry
+; CHECK-FP16-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-FP16-GI-NEXT: mov h1, v0.h[1]
+; CHECK-FP16-GI-NEXT: fcvtzs x8, h0
+; CHECK-FP16-GI-NEXT: fcvtzs x9, h1
+; CHECK-FP16-GI-NEXT: asr x10, x8, #63
+; CHECK-FP16-GI-NEXT: cmp x10, #1
+; CHECK-FP16-GI-NEXT: cset w12, lt
+; CHECK-FP16-GI-NEXT: asr x11, x9, #63
+; CHECK-FP16-GI-NEXT: csel w12, wzr, w12, eq
+; CHECK-FP16-GI-NEXT: cmp x11, #1
+; CHECK-FP16-GI-NEXT: cset w13, lt
+; CHECK-FP16-GI-NEXT: csel w13, wzr, w13, eq
+; CHECK-FP16-GI-NEXT: tst w12, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x10, x10, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w13, #0x1
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: csinc x11, x11, xzr, ne
+; CHECK-FP16-GI-NEXT: cmp x8, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x10, #0
+; CHECK-FP16-GI-NEXT: cset w10, gt
+; CHECK-FP16-GI-NEXT: csel w10, w12, w10, eq
+; CHECK-FP16-GI-NEXT: cmp x9, #0
+; CHECK-FP16-GI-NEXT: cset w12, hi
+; CHECK-FP16-GI-NEXT: cmp x11, #0
+; CHECK-FP16-GI-NEXT: cset w11, gt
+; CHECK-FP16-GI-NEXT: csel w11, w12, w11, eq
+; CHECK-FP16-GI-NEXT: tst w10, #0x1
+; CHECK-FP16-GI-NEXT: csel x8, x8, xzr, ne
+; CHECK-FP16-GI-NEXT: tst w11, #0x1
+; CHECK-FP16-GI-NEXT: fmov d0, x8
+; CHECK-FP16-GI-NEXT: csel x9, x9, xzr, ne
+; CHECK-FP16-GI-NEXT: mov v0.d[1], x9
+; CHECK-FP16-GI-NEXT: ret
entry:
%conv = fptosi <2 x half> %x to <2 x i128>
%spec.store.select = call <2 x i128> @llvm.smin.v2i128(<2 x i128> %conv, <2 x i128> <i128 18446744073709551616, i128 18446744073709551616>)
diff --git a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
index 9c21d2bf083a2..4f9610c63cf63 100644
--- a/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptosi-sat-vector.ll
@@ -1850,21 +1850,11 @@ define <4 x i13> @test_signed_v4f32_v4i13(<4 x float> %f) {
}
define <4 x i16> @test_signed_v4f32_v4i16(<4 x float> %f) {
-; CHECK-SD-LABEL: test_signed_v4f32_v4i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-SD-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_signed_v4f32_v4i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.4s, #127, msl #8
-; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-GI-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_signed_v4f32_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%x = call <4 x i16> @llvm.fptosi.sat.v4f32.v4i16(<4 x float> %f)
ret <4 x i16> %x
}
@@ -3008,12 +2998,8 @@ define <4 x i16> @test_signed_v4f16_v4i16(<4 x half> %f) {
; CHECK-GI-CVT-LABEL: test_signed_v4f16_v4i16:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: movi v1.4s, #127, msl #8
; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-CVT-NEXT: sqxtn v0.4h, v0.4s
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_signed_v4f16_v4i16:
@@ -3636,12 +3622,8 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
;
; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i8:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v1.8h, #127
; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: mvni v2.8h, #127
-; CHECK-GI-FP16-NEXT: smin v0.8h, v0.8h, v1.8h
-; CHECK-GI-FP16-NEXT: smax v0.8h, v0.8h, v2.8h
-; CHECK-GI-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-FP16-NEXT: sqxtn v0.8b, v0.8h
; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i8> @llvm.fptosi.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x
@@ -3717,17 +3699,12 @@ define <8 x i16> @test_signed_v8f16_v8i16(<8 x half> %f) {
;
; CHECK-GI-CVT-LABEL: test_signed_v8f16_v8i16:
; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v1.4s, v0.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-CVT-NEXT: movi v1.4s, #127, msl #8
-; CHECK-GI-CVT-NEXT: fcvtzs v2.4s, v2.4s
-; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: smin v2.4s, v2.4s, v1.4s
-; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: mvni v1.4s, #127, msl #8
-; CHECK-GI-CVT-NEXT: smax v2.4s, v2.4s, v1.4s
-; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-GI-CVT-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-GI-CVT-NEXT: fcvtzs v2.4s, v0.4s
+; CHECK-GI-CVT-NEXT: sqxtn v0.4h, v1.4s
+; CHECK-GI-CVT-NEXT: sqxtn2 v0.8h, v2.4s
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_signed_v8f16_v8i16:
@@ -4681,26 +4658,13 @@ define <16 x i8> @test_signed_v16f32_v16i8(<16 x float> %f) {
}
define <8 x i16> @test_signed_v8f32_v8i16(<8 x float> %f) {
-; CHECK-SD-LABEL: test_signed_v8f32_v8i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-SD-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-SD-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: sqxtn2 v0.8h, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_signed_v8f32_v8i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.4s, #127, msl #8
-; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-GI-NEXT: smin v0.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: smin v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: mvni v2.4s, #127, msl #8
-; CHECK-GI-NEXT: smax v0.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_signed_v8f32_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzs v0.4s, v0.4s
+; CHECK-NEXT: fcvtzs v1.4s, v1.4s
+; CHECK-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-NEXT: sqxtn2 v0.8h, v1.4s
+; CHECK-NEXT: ret
%x = call <8 x i16> @llvm.fptosi.sat.v8f32.v8i16(<8 x float> %f)
ret <8 x i16> %x
}
@@ -4720,22 +4684,14 @@ define <16 x i16> @test_signed_v16f32_v16i16(<16 x float> %f) {
;
; CHECK-GI-LABEL: test_signed_v16f32_v16i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v4.4s, #127, msl #8
; CHECK-GI-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-NEXT: fcvtzs v1.4s, v1.4s
; CHECK-GI-NEXT: fcvtzs v2.4s, v2.4s
+; CHECK-GI-NEXT: fcvtzs v4.4s, v1.4s
; CHECK-GI-NEXT: fcvtzs v3.4s, v3.4s
-; CHECK-GI-NEXT: mvni v5.4s, #127, msl #8
-; CHECK-GI-NEXT: smin v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: smin v1.4s, v1.4s, v4.4s
-; CHECK-GI-NEXT: smin v2.4s, v2.4s, v4.4s
-; CHECK-GI-NEXT: smin v3.4s, v3.4s, v4.4s
-; CHECK-GI-NEXT: smax v0.4s, v0.4s, v5.4s
-; CHECK-GI-NEXT: smax v1.4s, v1.4s, v5.4s
-; CHECK-GI-NEXT: smax v2.4s, v2.4s, v5.4s
-; CHECK-GI-NEXT: smax v3.4s, v3.4s, v5.4s
-; CHECK-GI-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: uzp1 v1.8h, v2.8h, v3.8h
+; CHECK-GI-NEXT: sqxtn v0.4h, v0.4s
+; CHECK-GI-NEXT: sqxtn v1.4h, v2.4s
+; CHECK-GI-NEXT: sqxtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: sqxtn2 v1.8h, v3.4s
; CHECK-GI-NEXT: ret
%x = call <16 x i16> @llvm.fptosi.sat.v16f32.v16i16(<16 x float> %f)
ret <16 x i16> %x
@@ -4804,15 +4760,10 @@ define <16 x i8> @test_signed_v16f16_v16i8(<16 x half> %f) {
;
; CHECK-GI-FP16-LABEL: test_signed_v16f16_v16i8:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v2.8h, #127
; CHECK-GI-FP16-NEXT: fcvtzs v0.8h, v0.8h
; CHECK-GI-FP16-NEXT: fcvtzs v1.8h, v1.8h
-; CHECK-GI-FP16-NEXT: mvni v3.8h, #127
-; CHECK-GI-FP16-NEXT: smin v0.8h, v0.8h, v2.8h
-; CHECK-GI-FP16-NEXT: smin v1.8h, v1.8h, v2.8h
-; CHECK-GI-FP16-NEXT: smax v0.8h, v0.8h, v3.8h
-; CHECK-GI-FP16-NEXT: smax v1.8h, v1.8h, v3.8h
-; CHECK-GI-FP16-NEXT: uzp1 v0.16b, v0.16b, v1.16b
+; CHECK-GI-FP16-NEXT: sqxtn v0.8b, v0.8h
+; CHECK-GI-FP16-NEXT: sqxtn2 v0.16b, v1.8h
; CHECK-GI-FP16-NEXT: ret
%x = call <16 x i8> @llvm.fptosi.sat.v16f16.v16i8(<16 x half> %f)
ret <16 x i8> %x
@@ -4843,26 +4794,18 @@ define <16 x i16> @test_signed_v16f16_v16i16(<16 x half> %f) {
;
; CHECK-GI-CVT-LABEL: test_signed_v16f16_v16i16:
; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v3.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v3.4s, v1.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-CVT-NEXT: fcvtl v4.4s, v1.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v1.4s, v1.8h
-; CHECK-GI-CVT-NEXT: movi v2.4s, #127, msl #8
-; CHECK-GI-CVT-NEXT: mvni v5.4s, #127, msl #8
+; CHECK-GI-CVT-NEXT: fcvtzs v2.4s, v2.4s
; CHECK-GI-CVT-NEXT: fcvtzs v3.4s, v3.4s
-; CHECK-GI-CVT-NEXT: fcvtzs v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: fcvtzs v4.4s, v4.4s
-; CHECK-GI-CVT-NEXT: fcvtzs v1.4s, v1.4s
-; CHECK-GI-CVT-NEXT: smin v3.4s, v3.4s, v2.4s
-; CHECK-GI-CVT-NEXT: smin v0.4s, v0.4s, v2.4s
-; CHECK-GI-CVT-NEXT: smin v4.4s, v4.4s, v2.4s
-; CHECK-GI-CVT-NEXT: smin v1.4s, v1.4s, v2.4s
-; CHECK-GI-CVT-NEXT: smax v2.4s, v3.4s, v5.4s
-; CHECK-GI-CVT-NEXT: smax v0.4s, v0.4s, v5.4s
-; CHECK-GI-CVT-NEXT: smax v3.4s, v4.4s, v5.4s
-; CHECK-GI-CVT-NEXT: smax v1.4s, v1.4s, v5.4s
-; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
-; CHECK-GI-CVT-NEXT: uzp1 v1.8h, v3.8h, v1.8h
+; CHECK-GI-CVT-NEXT: fcvtzs v4.4s, v0.4s
+; CHECK-GI-CVT-NEXT: fcvtzs v5.4s, v1.4s
+; CHECK-GI-CVT-NEXT: sqxtn v0.4h, v2.4s
+; CHECK-GI-CVT-NEXT: sqxtn v1.4h, v3.4s
+; CHECK-GI-CVT-NEXT: sqxtn2 v0.8h, v4.4s
+; CHECK-GI-CVT-NEXT: sqxtn2 v1.8h, v5.4s
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_signed_v16f16_v16i16:
diff --git a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
index 44847a41287d6..93a735babd68b 100644
--- a/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AArch64/fptoui-sat-vector.ll
@@ -1541,19 +1541,11 @@ define <4 x i13> @test_unsigned_v4f32_v4i13(<4 x float> %f) {
}
define <4 x i16> @test_unsigned_v4f32_v4i16(<4 x float> %f) {
-; CHECK-SD-LABEL: test_unsigned_v4f32_v4i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-SD-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_unsigned_v4f32_v4i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-GI-NEXT: xtn v0.4h, v0.4s
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_unsigned_v4f32_v4i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-NEXT: ret
%x = call <4 x i16> @llvm.fptoui.sat.v4f32.v4i16(<4 x float> %f)
ret <4 x i16> %x
}
@@ -2461,10 +2453,8 @@ define <4 x i16> @test_unsigned_v4f16_v4i16(<4 x half> %f) {
; CHECK-GI-CVT-LABEL: test_unsigned_v4f16_v4i16:
; CHECK-GI-CVT: // %bb.0:
; CHECK-GI-CVT-NEXT: fcvtl v0.4s, v0.4h
-; CHECK-GI-CVT-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-GI-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: xtn v0.4h, v0.4s
+; CHECK-GI-CVT-NEXT: uqxtn v0.4h, v0.4s
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_unsigned_v4f16_v4i16:
@@ -2991,10 +2981,8 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
;
; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i8:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v1.2d, #0xff00ff00ff00ff
; CHECK-GI-FP16-NEXT: fcvtzu v0.8h, v0.8h
-; CHECK-GI-FP16-NEXT: umin v0.8h, v0.8h, v1.8h
-; CHECK-GI-FP16-NEXT: xtn v0.8b, v0.8h
+; CHECK-GI-FP16-NEXT: uqxtn v0.8b, v0.8h
; CHECK-GI-FP16-NEXT: ret
%x = call <8 x i8> @llvm.fptoui.sat.v8f16.v8i8(<8 x half> %f)
ret <8 x i8> %x
@@ -3060,14 +3048,12 @@ define <8 x i16> @test_unsigned_v8f16_v8i16(<8 x half> %f) {
;
; CHECK-GI-CVT-LABEL: test_unsigned_v8f16_v8i16:
; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v1.4s, v0.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-CVT-NEXT: movi v1.2d, #0x00ffff0000ffff
-; CHECK-GI-CVT-NEXT: fcvtzu v2.4s, v2.4s
-; CHECK-GI-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: umin v2.4s, v2.4s, v1.4s
-; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v1.4s
-; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v2.8h, v0.8h
+; CHECK-GI-CVT-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-GI-CVT-NEXT: fcvtzu v2.4s, v0.4s
+; CHECK-GI-CVT-NEXT: uqxtn v0.4h, v1.4s
+; CHECK-GI-CVT-NEXT: uqxtn2 v0.8h, v2.4s
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_unsigned_v8f16_v8i16:
@@ -3865,23 +3851,13 @@ define <16 x i8> @test_unsigned_v16f32_v16i8(<16 x float> %f) {
}
define <8 x i16> @test_unsigned_v8f32_v8i16(<8 x float> %f) {
-; CHECK-SD-LABEL: test_unsigned_v8f32_v8i16:
-; CHECK-SD: // %bb.0:
-; CHECK-SD-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-SD-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-SD-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-SD-NEXT: uqxtn2 v0.8h, v1.4s
-; CHECK-SD-NEXT: ret
-;
-; CHECK-GI-LABEL: test_unsigned_v8f32_v8i16:
-; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v2.2d, #0x00ffff0000ffff
-; CHECK-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-GI-NEXT: umin v0.4s, v0.4s, v2.4s
-; CHECK-GI-NEXT: umin v1.4s, v1.4s, v2.4s
-; CHECK-GI-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: ret
+; CHECK-LABEL: test_unsigned_v8f32_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: fcvtzu v0.4s, v0.4s
+; CHECK-NEXT: fcvtzu v1.4s, v1.4s
+; CHECK-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-NEXT: uqxtn2 v0.8h, v1.4s
+; CHECK-NEXT: ret
%x = call <8 x i16> @llvm.fptoui.sat.v8f32.v8i16(<8 x float> %f)
ret <8 x i16> %x
}
@@ -3901,17 +3877,14 @@ define <16 x i16> @test_unsigned_v16f32_v16i16(<16 x float> %f) {
;
; CHECK-GI-LABEL: test_unsigned_v16f32_v16i16:
; CHECK-GI: // %bb.0:
-; CHECK-GI-NEXT: movi v4.2d, #0x00ffff0000ffff
; CHECK-GI-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-NEXT: fcvtzu v1.4s, v1.4s
; CHECK-GI-NEXT: fcvtzu v2.4s, v2.4s
+; CHECK-GI-NEXT: fcvtzu v4.4s, v1.4s
; CHECK-GI-NEXT: fcvtzu v3.4s, v3.4s
-; CHECK-GI-NEXT: umin v0.4s, v0.4s, v4.4s
-; CHECK-GI-NEXT: umin v1.4s, v1.4s, v4.4s
-; CHECK-GI-NEXT: umin v2.4s, v2.4s, v4.4s
-; CHECK-GI-NEXT: umin v3.4s, v3.4s, v4.4s
-; CHECK-GI-NEXT: uzp1 v0.8h, v0.8h, v1.8h
-; CHECK-GI-NEXT: uzp1 v1.8h, v2.8h, v3.8h
+; CHECK-GI-NEXT: uqxtn v0.4h, v0.4s
+; CHECK-GI-NEXT: uqxtn v1.4h, v2.4s
+; CHECK-GI-NEXT: uqxtn2 v0.8h, v4.4s
+; CHECK-GI-NEXT: uqxtn2 v1.8h, v3.4s
; CHECK-GI-NEXT: ret
%x = call <16 x i16> @llvm.fptoui.sat.v16f32.v16i16(<16 x float> %f)
ret <16 x i16> %x
@@ -3970,12 +3943,10 @@ define <16 x i8> @test_unsigned_v16f16_v16i8(<16 x half> %f) {
;
; CHECK-GI-FP16-LABEL: test_unsigned_v16f16_v16i8:
; CHECK-GI-FP16: // %bb.0:
-; CHECK-GI-FP16-NEXT: movi v2.2d, #0xff00ff00ff00ff
; CHECK-GI-FP16-NEXT: fcvtzu v0.8h, v0.8h
; CHECK-GI-FP16-NEXT: fcvtzu v1.8h, v1.8h
-; CHECK-GI-FP16-NEXT: umin v0.8h, v0.8h, v2.8h
-; CHECK-GI-FP16-NEXT: umin v1.8h, v1.8h, v2.8h
-; CHECK-GI-FP16-NEXT: uzp1 v0.16b, v0.16b, v1.16b
+; CHECK-GI-FP16-NEXT: uqxtn v0.8b, v0.8h
+; CHECK-GI-FP16-NEXT: uqxtn2 v0.16b, v1.8h
; CHECK-GI-FP16-NEXT: ret
%x = call <16 x i8> @llvm.fptoui.sat.v16f16.v16i8(<16 x half> %f)
ret <16 x i8> %x
@@ -4006,21 +3977,18 @@ define <16 x i16> @test_unsigned_v16f16_v16i16(<16 x half> %f) {
;
; CHECK-GI-CVT-LABEL: test_unsigned_v16f16_v16i16:
; CHECK-GI-CVT: // %bb.0:
-; CHECK-GI-CVT-NEXT: fcvtl v3.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v2.4s, v0.4h
+; CHECK-GI-CVT-NEXT: fcvtl v3.4s, v1.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v0.4s, v0.8h
-; CHECK-GI-CVT-NEXT: fcvtl v4.4s, v1.4h
; CHECK-GI-CVT-NEXT: fcvtl2 v1.4s, v1.8h
-; CHECK-GI-CVT-NEXT: movi v2.2d, #0x00ffff0000ffff
+; CHECK-GI-CVT-NEXT: fcvtzu v2.4s, v2.4s
; CHECK-GI-CVT-NEXT: fcvtzu v3.4s, v3.4s
-; CHECK-GI-CVT-NEXT: fcvtzu v0.4s, v0.4s
-; CHECK-GI-CVT-NEXT: fcvtzu v4.4s, v4.4s
-; CHECK-GI-CVT-NEXT: fcvtzu v1.4s, v1.4s
-; CHECK-GI-CVT-NEXT: umin v3.4s, v3.4s, v2.4s
-; CHECK-GI-CVT-NEXT: umin v0.4s, v0.4s, v2.4s
-; CHECK-GI-CVT-NEXT: umin v4.4s, v4.4s, v2.4s
-; CHECK-GI-CVT-NEXT: umin v1.4s, v1.4s, v2.4s
-; CHECK-GI-CVT-NEXT: uzp1 v0.8h, v3.8h, v0.8h
-; CHECK-GI-CVT-NEXT: uzp1 v1.8h, v4.8h, v1.8h
+; CHECK-GI-CVT-NEXT: fcvtzu v4.4s, v0.4s
+; CHECK-GI-CVT-NEXT: fcvtzu v5.4s, v1.4s
+; CHECK-GI-CVT-NEXT: uqxtn v0.4h, v2.4s
+; CHECK-GI-CVT-NEXT: uqxtn v1.4h, v3.4s
+; CHECK-GI-CVT-NEXT: uqxtn2 v0.8h, v4.4s
+; CHECK-GI-CVT-NEXT: uqxtn2 v1.8h, v5.4s
; CHECK-GI-CVT-NEXT: ret
;
; CHECK-GI-FP16-LABEL: test_unsigned_v16f16_v16i16:
diff --git a/llvm/test/CodeGen/AArch64/qmovn.ll b/llvm/test/CodeGen/AArch64/qmovn.ll
index 2685ea9fb5d20..bd99c1ca81d3a 100644
--- a/llvm/test/CodeGen/AArch64/qmovn.ll
+++ b/llvm/test/CodeGen/AArch64/qmovn.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs %s -o - | FileCheck %s
+; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs -global-isel=0 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD
+; RUN: llc -mtriple=aarch64-none-elf -verify-machineinstrs -global-isel=1 %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI
define <4 x i16> @vqmovni32_smaxmin(<4 x i32> %s0) {
; CHECK-LABEL: vqmovni32_smaxmin:
@@ -425,16 +426,31 @@ entry:
; Type support varification - not supported with saturated value
; i64 -> i16
define <4 x i16> @sminsmax_range_unsigned_i64_to_i16(<2 x i16> %x, <2 x i64> %y) {
-; CHECK-LABEL: sminsmax_range_unsigned_i64_to_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: cmgt v2.2d, v1.2d, #0
-; CHECK-NEXT: movi v3.2d, #0x0000000000ffff
-; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
-; CHECK-NEXT: cmgt v2.2d, v3.2d, v1.2d
-; CHECK-NEXT: bif v1.16b, v3.16b, v2.16b
-; CHECK-NEXT: xtn v1.2s, v1.2d
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v1.4h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_unsigned_i64_to_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: cmgt v2.2d, v1.2d, #0
+; CHECK-SD-NEXT: movi v3.2d, #0x0000000000ffff
+; CHECK-SD-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: cmgt v2.2d, v3.2d, v1.2d
+; CHECK-SD-NEXT: bif v1.16b, v3.16b, v2.16b
+; CHECK-SD-NEXT: xtn v1.2s, v1.2d
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_unsigned_i64_to_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: cmgt v2.2d, v1.2d, #0
+; CHECK-GI-NEXT: movi v3.2d, #0x0000000000ffff
+; CHECK-GI-NEXT: and v1.16b, v1.16b, v2.16b
+; CHECK-GI-NEXT: cmgt v2.2d, v3.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v3.16b, v2.16b
+; CHECK-GI-NEXT: xtn v1.2s, v1.2d
+; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%smax = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> zeroinitializer)
%smin = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %smax, <2 x i64> <i64 65535, i64 65535>)
@@ -444,19 +460,37 @@ entry:
}
define <4 x i16> @sminsmax_range_signed_i64_to_i16(<2 x i16> %x, <2 x i64> %y) {
-; CHECK-LABEL: sminsmax_range_signed_i64_to_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mov x8, #-32768 // =0xffffffffffff8000
-; CHECK-NEXT: dup v2.2d, x8
-; CHECK-NEXT: mov w8, #32767 // =0x7fff
-; CHECK-NEXT: cmgt v3.2d, v1.2d, v2.2d
-; CHECK-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-NEXT: dup v2.2d, x8
-; CHECK-NEXT: cmgt v3.2d, v2.2d, v1.2d
-; CHECK-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-NEXT: xtn v1.2s, v1.2d
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v1.4h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_signed_i64_to_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mov x8, #-32768 // =0xffffffffffff8000
+; CHECK-SD-NEXT: dup v2.2d, x8
+; CHECK-SD-NEXT: mov w8, #32767 // =0x7fff
+; CHECK-SD-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-SD-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: dup v2.2d, x8
+; CHECK-SD-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-SD-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: xtn v1.2s, v1.2d
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_signed_i64_to_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: adrp x8, .LCPI31_1
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI31_1]
+; CHECK-GI-NEXT: adrp x8, .LCPI31_0
+; CHECK-GI-NEXT: cmgt v3.2d, v1.2d, v2.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI31_0]
+; CHECK-GI-NEXT: cmgt v3.2d, v2.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: xtn v1.2s, v1.2d
+; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%smax = call <2 x i64> @llvm.smax.v2i64(<2 x i64> %y, <2 x i64> <i64 -32768, i64 -32768>)
%smin = call <2 x i64> @llvm.smin.v2i64(<2 x i64> %smax, <2 x i64> <i64 32767, i64 32767>)
@@ -466,14 +500,27 @@ entry:
}
define <4 x i16> @umin_range_unsigned_i64_to_i16(<2 x i16> %x, <2 x i64> %y) {
-; CHECK-LABEL: umin_range_unsigned_i64_to_i16:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.2d, #0x0000000000ffff
-; CHECK-NEXT: cmhi v3.2d, v2.2d, v1.2d
-; CHECK-NEXT: bif v1.16b, v2.16b, v3.16b
-; CHECK-NEXT: xtn v1.2s, v1.2d
-; CHECK-NEXT: uzp1 v0.4h, v0.4h, v1.4h
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: umin_range_unsigned_i64_to_i16:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.2d, #0x0000000000ffff
+; CHECK-SD-NEXT: cmhi v3.2d, v2.2d, v1.2d
+; CHECK-SD-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-SD-NEXT: xtn v1.2s, v1.2d
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v1.4h
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: umin_range_unsigned_i64_to_i16:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0x0000000000ffff
+; CHECK-GI-NEXT: cmhi v3.2d, v2.2d, v1.2d
+; CHECK-GI-NEXT: bif v1.16b, v2.16b, v3.16b
+; CHECK-GI-NEXT: xtn v1.2s, v1.2d
+; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h
+; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%umin = call <2 x i64> @llvm.umin.v2i64(<2 x i64> %y, <2 x i64> <i64 65535, i64 65535>)
%trunc = trunc <2 x i64> %umin to <2 x i16>
@@ -483,15 +530,29 @@ entry:
; i32 -> i8
define <8 x i8> @sminsmax_range_unsigned_i64_to_i8(<4 x i8> %x, <4 x i32> %y) {
-; CHECK-LABEL: sminsmax_range_unsigned_i64_to_i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.2d, #0000000000000000
-; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: movi v2.2d, #0x0000ff000000ff
-; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: xtn v1.4h, v1.4s
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_unsigned_i64_to_i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.2d, #0000000000000000
+; CHECK-SD-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-SD-NEXT: movi v2.2d, #0x0000ff000000ff
+; CHECK-SD-NEXT: smin v1.4s, v1.4s, v2.4s
+; CHECK-SD-NEXT: xtn v1.4h, v1.4s
+; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_unsigned_i64_to_i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0000000000000000
+; CHECK-GI-NEXT: movi v3.2d, #0x0000ff000000ff
+; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: smin v1.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: xtn v1.4h, v1.4s
+; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%smax = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> zeroinitializer)
%smin = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %smax, <4 x i32> <i32 255, i32 255, i32 255, i32 255>)
@@ -501,15 +562,29 @@ entry:
}
define <8 x i8> @sminsmax_range_signed_i32_to_i8(<4 x i8> %x, <4 x i32> %y) {
-; CHECK-LABEL: sminsmax_range_signed_i32_to_i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: mvni v2.4s, #127
-; CHECK-NEXT: smax v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: movi v2.4s, #127
-; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: xtn v1.4h, v1.4s
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: sminsmax_range_signed_i32_to_i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: mvni v2.4s, #127
+; CHECK-SD-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-SD-NEXT: movi v2.4s, #127
+; CHECK-SD-NEXT: smin v1.4s, v1.4s, v2.4s
+; CHECK-SD-NEXT: xtn v1.4h, v1.4s
+; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: sminsmax_range_signed_i32_to_i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: mvni v2.4s, #127
+; CHECK-GI-NEXT: movi v3.4s, #127
+; CHECK-GI-NEXT: smax v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: smin v1.4s, v1.4s, v3.4s
+; CHECK-GI-NEXT: xtn v1.4h, v1.4s
+; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%smax = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %y, <4 x i32> <i32 -128, i32 -128, i32 -128, i32 -128>)
%smin = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %smax, <4 x i32> <i32 127, i32 127, i32 127, i32 127>)
@@ -519,13 +594,25 @@ entry:
}
define <8 x i8> @umin_range_unsigned_i32_to_i8(<4 x i8> %x, <4 x i32> %y) {
-; CHECK-LABEL: umin_range_unsigned_i32_to_i8:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v2.2d, #0x0000ff000000ff
-; CHECK-NEXT: umin v1.4s, v1.4s, v2.4s
-; CHECK-NEXT: xtn v1.4h, v1.4s
-; CHECK-NEXT: uzp1 v0.8b, v0.8b, v1.8b
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: umin_range_unsigned_i32_to_i8:
+; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v2.2d, #0x0000ff000000ff
+; CHECK-SD-NEXT: umin v1.4s, v1.4s, v2.4s
+; CHECK-SD-NEXT: xtn v1.4h, v1.4s
+; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v1.8b
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: umin_range_unsigned_i32_to_i8:
+; CHECK-GI: // %bb.0: // %entry
+; CHECK-GI-NEXT: movi v2.2d, #0x0000ff000000ff
+; CHECK-GI-NEXT: umin v1.4s, v1.4s, v2.4s
+; CHECK-GI-NEXT: xtn v1.4h, v1.4s
+; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b
+; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b
+; CHECK-GI-NEXT: fmov w8, s1
+; CHECK-GI-NEXT: mov v0.s[1], w8
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0
+; CHECK-GI-NEXT: ret
entry:
%umin = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %y, <4 x i32> <i32 255, i32 255, i32 255, i32 255>)
%trunc = trunc <4 x i32> %umin to <4 x i8>
diff --git a/llvm/test/CodeGen/AArch64/truncsat.ll b/llvm/test/CodeGen/AArch64/truncsat.ll
deleted file mode 100644
index 19779aba2697e..0000000000000
--- a/llvm/test/CodeGen/AArch64/truncsat.ll
+++ /dev/null
@@ -1,79 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
-; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel=1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
-
-
-define <4 x i16> @ssats_1(<4 x i32> %x) {
-; CHECK-LABEL: ssats_1:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-NEXT: ret
-entry:
- %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
- %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
- %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
- ret <4 x i16> %conv6
-}
-
-define <4 x i16> @ssats_2(<4 x i32> %x) {
-; CHECK-LABEL: ssats_2:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtn v0.4h, v0.4s
-; CHECK-NEXT: ret
-entry:
- %spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> <i32 -32768, i32 -32768, i32 -32768, i32 -32768>)
- %spec.store.select7 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 32767, i32 32767, i32 32767, i32 32767>)
- %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
- ret <4 x i16> %conv6
-}
-
-define <4 x i16> @ssatu_1(<4 x i32> %x) {
-; CHECK-LABEL: ssatu_1:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-NEXT: ret
-entry:
- %spec.store.select = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %x, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
- %spec.store.select7 = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %spec.store.select, <4 x i32> zeroinitializer)
- %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
- ret <4 x i16> %conv6
-}
-
-define <4 x i16> @ssatu_2(<4 x i32> %x) {
-; CHECK-LABEL: ssatu_2:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-NEXT: ret
-entry:
- %spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> zeroinitializer)
- %spec.store.select7 = call <4 x i32> @llvm.smin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
- %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
- ret <4 x i16> %conv6
-}
-
-define <4 x i16> @ssatu_3(<4 x i32> %x) {
-; CHECK-LABEL: ssatu_3:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: sqxtun v0.4h, v0.4s
-; CHECK-NEXT: ret
-entry:
- %spec.store.select = call <4 x i32> @llvm.smax.v4i32(<4 x i32> %x, <4 x i32> zeroinitializer)
- %spec.store.select7 = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %spec.store.select, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
- %conv6 = trunc <4 x i32> %spec.store.select7 to <4 x i16>
- ret <4 x i16> %conv6
-}
-
-define <4 x i16> @usatu(<4 x i32> %x) {
-; CHECK-LABEL: usatu:
-; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: uqxtn v0.4h, v0.4s
-; CHECK-NEXT: ret
-entry:
- %spec.store.select = call <4 x i32> @llvm.umin.v4i32(<4 x i32> %x, <4 x i32> <i32 65535, i32 65535, i32 65535, i32 65535>)
- %conv6 = trunc <4 x i32> %spec.store.select to <4 x i16>
- ret <4 x i16> %conv6
-}
-
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; CHECK-GI: {{.*}}
-; CHECK-SD: {{.*}}
>From d4345fd26c1a23b00f043e662192f913c995323a Mon Sep 17 00:00:00 2001
From: Yu Li <yu.li at arm.com>
Date: Wed, 6 Aug 2025 09:49:36 +0000
Subject: [PATCH 3/3] formatting
---
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index 11f7872f566a5..7ca883918ca6a 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -5857,13 +5857,15 @@ bool CombinerHelper::matchTruncSSatS(MachineInstr &MI,
APInt SignedMax = APInt::getSignedMaxValue(NumDstBits).sext(NumSrcBits);
APInt SignedMin = APInt::getSignedMinValue(NumDstBits).sext(NumSrcBits);
if (isLegal({TargetOpcode::G_TRUNC_SSAT_S, {DstTy, SrcTy}})) {
- if (mi_match(Src, MRI,
- m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(SignedMin)),
- m_SpecificICstOrSplat(SignedMax))))
+ if (mi_match(
+ Src, MRI,
+ m_GSMin(m_GSMax(m_Reg(MatchInfo), m_SpecificICstOrSplat(SignedMin)),
+ m_SpecificICstOrSplat(SignedMax))))
return true;
- if (mi_match(Src, MRI,
- m_GSMax(m_GSMin(m_Reg(MatchInfo), m_SpecificICstOrSplat(SignedMax)),
- m_SpecificICstOrSplat(SignedMin))))
+ if (mi_match(
+ Src, MRI,
+ m_GSMax(m_GSMin(m_Reg(MatchInfo), m_SpecificICstOrSplat(SignedMax)),
+ m_SpecificICstOrSplat(SignedMin))))
return true;
}
return false;
@@ -5893,7 +5895,8 @@ bool CombinerHelper::matchTruncSSatU(MachineInstr &MI,
m_SpecificICstOrSplat(UnsignedMax))))
return true;
if (mi_match(Src, MRI,
- m_GSMax(m_GSMin(m_Reg(MatchInfo), m_SpecificICstOrSplat(UnsignedMax)),
+ m_GSMax(m_GSMin(m_Reg(MatchInfo),
+ m_SpecificICstOrSplat(UnsignedMax)),
m_SpecificICstOrSplat(0))))
return true;
if (mi_match(Src, MRI,
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