[llvm] Co-issue packed instructions by unpacking (PR #151704)

[Jeffrey Byrnes via llvm-commits]

================
@@ -225,6 +247,313 @@ bool GCNPreRAOptimizationsImpl::processReg(Register Reg) {
   return true;
 }
 
+bool GCNPreRAOptimizationsImpl::isUnpackingSupportedInstr(MachineInstr &MI) const {
+  unsigned Opcode = MI.getOpcode();
+  switch (Opcode) {
+    case AMDGPU::V_PK_ADD_F32:
+    case AMDGPU::V_PK_MUL_F32:
+      return true;
+
+    default:
+      return false;
+
+  }
+}
+
+uint16_t GCNPreRAOptimizationsImpl::mapToUnpackedOpcode(MachineInstr &I) {
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jrbyrnes wrote:

List is incomplete -- see the change in SIInstrInfo.cpp in this commit https://github.com/llvm/llvm-project/pull/132432/commits/55b02e0b0ca7a74c51e6ef43f29e66261a514e62 for the list of non-coissue instructions.

There are several V_PK instructions in that list which have scalar equivalents that are not included in this mapping (e.g. `V_PK_MAX_I16` -> `V_MAX_I16_e64` )

https://github.com/llvm/llvm-project/pull/151704