[llvm] [WebAssembly] Add fold support for dot (PR #151775)

[Jasmine Tang via llvm-commits]

================
@@ -3436,6 +3439,53 @@ static SDValue performSETCCCombine(SDNode *N,
   return SDValue();
 }
 
+static SDValue performAddCombine(SDNode *N, SelectionDAG &DAG) {
+  assert(N->getOpcode() == ISD::ADD);
+  EVT VT = N->getValueType(0);
+  SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
+
+  if (VT != MVT::v4i32)
+    return SDValue();
+
+  auto IsShuffleWithMask = [](SDValue V, ArrayRef<int> ShuffleValue) {
+    if (V.getOpcode() != ISD::VECTOR_SHUFFLE)
+      return SDValue();
+    if (cast<ShuffleVectorSDNode>(V)->getMask() != ShuffleValue)
+      return SDValue();
+    return V;
+  };
+  auto ShuffleA = IsShuffleWithMask(N0, {0, 2, 4, 6});
+  auto ShuffleB = IsShuffleWithMask(N1, {1, 3, 5, 7});
+  // two SDValues must be muls
+  if (!ShuffleA || !ShuffleB)
+    return SDValue();
+
+  if (ShuffleA.getOperand(0) != ShuffleB.getOperand(0) ||
+      ShuffleA.getOperand(1) != ShuffleB.getOperand(1))
+    return SDValue();
+
+  auto IsMulExtend =
+      [](SDValue V, WebAssemblyISD::NodeType I) -> std::pair<SDValue, SDValue> {
+    if (V.getOpcode() != ISD::MUL)
+      return {};
+
+    auto V0 = V.getOperand(0), V1 = V.getOperand(1);
+    if (V0.getOpcode() != I || V1.getOpcode() != I)
+      return {};
+    return {V0.getOperand(0), V1.getOperand(0)};
+  };
+
+  auto [LowA, LowB] =
+      IsMulExtend(ShuffleA.getOperand(0), WebAssemblyISD::EXTEND_LOW_S);
----------------
badumbatish wrote:

SIGN_EXTEND nodes' last occurence is in the optimized lowered selection dag, where the dag a bit more complex compared to the vector-legalized selection dag

```
Optimized lowered selection DAG: %bb.0 'dot:entry'
SelectionDAG has 28 nodes:
      t4: v8i16 = WebAssemblyISD::ARGUMENT TargetConstant:i32<1>
    t6: v8i32 = sign_extend t4
      t2: v8i16 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>
    t5: v8i32 = sign_extend t2
  t7: v8i32 = mul nsw t6, t5
    t0: ch,glue = EntryToken
        t10: i32 = extract_vector_elt t7, Constant:i32<0>
        t12: i32 = extract_vector_elt t7, Constant:i32<2>
        t14: i32 = extract_vector_elt t7, Constant:i32<4>
        t16: i32 = extract_vector_elt t7, Constant:i32<6>
      t17: v4i32 = BUILD_VECTOR t10, t12, t14, t16
        t19: i32 = extract_vector_elt t7, Constant:i32<1>
        t21: i32 = extract_vector_elt t7, Constant:i32<3>
        t23: i32 = extract_vector_elt t7, Constant:i32<5>
        t25: i32 = extract_vector_elt t7, Constant:i32<7>
      t26: v4i32 = BUILD_VECTOR t19, t21, t23, t25
    t28: v4i32 = add t17, t26
  t29: ch = WebAssemblyISD::RETURN t
```

https://github.com/llvm/llvm-project/pull/151775