[llvm] [ARM] Fix inline asm register validation for vector types (PR #152175)

[Eli Friedman via llvm-commits]

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@@ -20350,8 +20350,10 @@ ARMTargetLowering::getSingleConstraintMatchWeight(
 static bool isIncompatibleReg(const MCPhysReg &PR, MVT VT) {
   if (PR == 0 || VT == MVT::Other)
     return false;
-  return (ARM::SPRRegClass.contains(PR) && VT != MVT::f32 && VT != MVT::i32) ||
-         (ARM::DPRRegClass.contains(PR) && VT != MVT::f64);
+  return (ARM::SPRRegClass.contains(PR) && VT != MVT::f32 && VT != MVT::i32 &&
+          !VT.is32BitVector()) ||
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efriedma-quic wrote:

Is it actually possible to hit the is32BitVector() case?  If it is, can you add a testcase?

https://github.com/llvm/llvm-project/pull/152175