[llvm] [ARM] Fix inline asm register validation for vector types (PR #152175)

[via llvm-commits]

https://github.com/eleviant created https://github.com/llvm/llvm-project/pull/152175

Patch allows following piece of code to be successfully compiled:
```
register uint8x8_t V asm("d3") = vdup_n_u8(0xff);
```

>From f4d8dcfdb0c9e641a910ad49efa862d5f5765daa Mon Sep 17 00:00:00 2001
From: Evgeny Leviant <eleviant at accesssoftek.com>
Date: Tue, 5 Aug 2025 17:46:08 +0200
Subject: [PATCH] [ARM] Fix inline asm register validation for vector types

Patch allows following piece of code to be successfully compiled:
```
register uint8x8_t V asm("d3") = vdup_n_u8(0xff);
```
---
 llvm/lib/Target/ARM/ARMISelLowering.cpp          |  6 ++++--
 llvm/test/CodeGen/ARM/bad-constraint.ll          |  6 ++++++
 llvm/test/CodeGen/ARM/inlineasm-vec-to-double.ll | 14 ++++++++++++++
 3 files changed, 24 insertions(+), 2 deletions(-)
 create mode 100644 llvm/test/CodeGen/ARM/inlineasm-vec-to-double.ll

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 7f8b4460bb814..7c84033671cce 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -20350,8 +20350,10 @@ ARMTargetLowering::getSingleConstraintMatchWeight(
 static bool isIncompatibleReg(const MCPhysReg &PR, MVT VT) {
   if (PR == 0 || VT == MVT::Other)
     return false;
-  return (ARM::SPRRegClass.contains(PR) && VT != MVT::f32 && VT != MVT::i32) ||
-         (ARM::DPRRegClass.contains(PR) && VT != MVT::f64);
+  return (ARM::SPRRegClass.contains(PR) && VT != MVT::f32 && VT != MVT::i32 &&
+          !VT.is32BitVector()) ||
+         (ARM::DPRRegClass.contains(PR) && VT != MVT::f64 &&
+          !VT.is64BitVector());
 }
 
 using RCPair = std::pair<unsigned, const TargetRegisterClass *>;
diff --git a/llvm/test/CodeGen/ARM/bad-constraint.ll b/llvm/test/CodeGen/ARM/bad-constraint.ll
index 9b8fcd576db5d..9de6bebdff441 100644
--- a/llvm/test/CodeGen/ARM/bad-constraint.ll
+++ b/llvm/test/CodeGen/ARM/bad-constraint.ll
@@ -1,6 +1,7 @@
 ; RUN: not llc -filetype=obj %s -o /dev/null 2>&1 | FileCheck %s
 ; CHECK:      error: couldn't allocate input reg for constraint '{d2}'
 ; CHECK-NEXT: error: couldn't allocate input reg for constraint '{s2}'
+; CHECK-NEXT: error: couldn't allocate input reg for constraint '{d3}'
 
 target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
 target triple = "armv8a-unknown-linux-gnueabihf"
@@ -23,3 +24,8 @@ entry:
   ret void
 }
 
+define void @_Z1dv() local_unnamed_addr {
+entry:
+  tail call void asm sideeffect "", "{d3}"(<16 x i8> undef)
+  ret void
+}
diff --git a/llvm/test/CodeGen/ARM/inlineasm-vec-to-double.ll b/llvm/test/CodeGen/ARM/inlineasm-vec-to-double.ll
new file mode 100644
index 0000000000000..0c01bb9ea6867
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/inlineasm-vec-to-double.ll
@@ -0,0 +1,14 @@
+; RUN: llc %s -filetype=asm -o - | FileCheck %s
+
+; CHECK: vmov.i8 d3, #0xff
+
+target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
+target triple = "armv8a-unknown-linux-gnueabihf"
+
+; Function Attrs: mustprogress noimplicitfloat nounwind
+define void @cvt_vec() local_unnamed_addr {
+entry:
+  tail call void asm sideeffect "", "{d3}"(<8 x i8> splat (i8 -1))
+  ret void
+}
+